ADC_ETC Global Control Register
ETC DMA control Register
ETC DONE0 and DONE1 IRQ State Register
ETC DONE_2 and DONE_ERR IRQ State Register
ETC_TRIG Chain 0/1 Register
ETC_TRIG Chain 2/3 Register
ETC_TRIG Chain 4/5 Register
ETC_TRIG Chain 6/7 Register
ETC_TRIG Counter Register
ETC_TRIG Control Register
ETC_TRIG Result Data 1/0 Register
ETC_TRIG Result Data 3/2 Register
ETC_TRIG Result Data 5/4 Register
ETC_TRIG Result Data 7/6 Register
ETC_TRIG Chain 0/1 Register
ETC_TRIG Chain 2/3 Register
ETC_TRIG Chain 4/5 Register
ETC_TRIG Chain 6/7 Register
ETC_TRIG Counter Register
ETC_TRIG Control Register
ETC_TRIG Result Data 1/0 Register
ETC_TRIG Result Data 3/2 Register
ETC_TRIG Result Data 5/4 Register
ETC_TRIG Result Data 7/6 Register
ETC_TRIG Chain 0/1 Register
ETC_TRIG Chain 2/3 Register
ETC_TRIG Chain 4/5 Register
ETC_TRIG Chain 6/7 Register
ETC_TRIG Counter Register
ETC_TRIG Control Register
ETC_TRIG Result Data 1/0 Register
ETC_TRIG Result Data 3/2 Register
ETC_TRIG Result Data 5/4 Register
ETC_TRIG Result Data 7/6 Register
ETC_TRIG Chain 0/1 Register
ETC_TRIG Chain 2/3 Register
ETC_TRIG Chain 4/5 Register
ETC_TRIG Chain 6/7 Register
ETC_TRIG Counter Register
ETC_TRIG Control Register
ETC_TRIG Result Data 1/0 Register
ETC_TRIG Result Data 3/2 Register
ETC_TRIG Result Data 5/4 Register
ETC_TRIG Result Data 7/6 Register