Module DLLCR

DLL Control Register 0

Modules

• DLLEN
  DLL calibration enable.
• DLLRESET
  Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation).
• OVRDEN
  Slave clock delay line delay cell number selection override enable.
• OVRDVAL
  Slave clock delay line delay cell number selection override value.
• SLVDLYTARGET
  The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). If serial root clock is >= 100 MHz, DLLEN set to 0x1, OVRDEN set to =0x0, then SLVDLYTARGET setting of 0xF is recommended.