Expand description
DMA Control Register, UARTDMACR
Structs§
- DMA Control Register, UARTDMACR
Type Aliases§
- Field
DMAONERR
reader - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. - Field
DMAONERR
writer - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. - Register
UARTDMACR
reader - Field
RXDMAE
reader - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. - Field
RXDMAE
writer - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. - Field
TXDMAE
reader - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. - Field
TXDMAE
writer - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. - Register
UARTDMACR
writer