Module fifo_st

Status register for inter-core FIFOs (mailboxes).
There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.
Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).
Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).
The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.

Structs

• FIFO_ST_SPEC
  Status register for inter-core FIFOs (mailboxes).
  There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.
  Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).
  Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).
  The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.

Type Aliases

• R
  Register FIFO_ST reader
• RDY_R
  Field RDY reader - Value is 1 if this core’s TX FIFO is not full (i.e. if FIFO_WR is ready for more data)
• ROE_R
  Field ROE reader - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.
• ROE_W
  Field ROE writer - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.
• VLD_R
  Field VLD reader - Value is 1 if this core’s RX FIFO is not empty (i.e. if FIFO_RD is valid)
• W
  Register FIFO_ST writer
• WOF_R
  Field WOF reader - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.
• WOF_W
  Field WOF writer - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.