Module LPCR

SNVS_LP Control Register

Modules

• BTN_PRESS_TIME
  This field configures the button press time out values for the PMIC Logic
• DEBOUNCE
  This field configures the amount of debounce time for the BTN input signal
• DP_EN
  Dumb PMIC Enabled When set, software can control the system power
• GPR_Z_DIS
  General Purpose Registers Zeroization Disable
• LPCALB_EN
  LP Calibration Enable When set, enables the SRTC calibration mechanism
• LPCALB_VAL
  LP Calibration Value Defines signed calibration value for SRTC
• LPTA_EN
  LP Time Alarm Enable When set, the SNVS functional interrupt is asserted if the LP Time Alarm Register is equal to the 32 MSBs of the secure real time counter
• LPWUI_EN
  LP Wake-Up Interrupt Enable This interrupt line should be connected to the external pin and is intended to inform the external chip about an SNVS_LP event (tamper event, MC rollover, SRTC rollover, or time alarm )
• MC_ENV
  Monotonic Counter Enabled and Valid When set, the MC can be incremented (by write transaction to the LPSMCMR or LPSMCLR)
• ON_TIME
  The ON_TIME field is used to configure the period of time after BTN is asserted before pmic_en_b is asserted to turn on the SoC power
• PK_EN
  PMIC On Request Enable The value written to PK_EN will be asserted on output signal snvs_lp_pk_en
• PK_OVERRIDE
  PMIC On Request Override The value written to PK_OVERRIDE will be asserted on output signal snvs_lp_pk_override
• PWR_GLITCH_EN
  Power Glitch Enable By default the detection of a power glitch does not cause the pmic_en_b signal to be asserted
• SRTC_ENV
  Secure Real Time Counter Enabled and Valid When set, the SRTC becomes operational
• SRTC_INV_EN
  If this bit is 1, in the case of a security violation the SRTC stops counting and the SRTC is invalidated (SRTC_ENV bit is cleared)
• TOP
  Turn off System Power Asserting this bit causes a signal to be sent to the Power Management IC to turn off the system power