Module CDCDR

CCM D1 Clock Divider Register

Modules

• SPDIF0_CLK_PODF
  Divider for spdif0 clock podf. Divider should be updated when output clock is gated.
• SPDIF0_CLK_PRED
  Divider for spdif0 clock pred. Divider should be updated when output clock is gated.
• SPDIF0_CLK_SEL
  Selector for spdif0 clock multiplexer