Expand description
DMA Control Register, UARTDMACR
Structs§
- DMA Control Register, UARTDMACR
Type Aliases§
- Field
DMAONERRreader - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. - Field
DMAONERRwriter - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. - Register
UARTDMACRreader - Field
RXDMAEreader - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. - Field
RXDMAEwriter - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. - Field
TXDMAEreader - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. - Field
TXDMAEwriter - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. - Register
UARTDMACRwriter