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#[repr(C)]
</span><span class="kw">pub struct </span>RegisterBlock {
proc0_nmi_mask: PROC0_NMI_MASK,
proc1_nmi_mask: PROC1_NMI_MASK,
proc_config: PROC_CONFIG,
proc_in_sync_bypass: PROC_IN_SYNC_BYPASS,
proc_in_sync_bypass_hi: PROC_IN_SYNC_BYPASS_HI,
dbgforce: DBGFORCE,
mempowerdown: MEMPOWERDOWN,
}
<span class="kw">impl </span>RegisterBlock {
<span class="attr">#[doc = <span class="string">"0x00 - Processor core 0 NMI source mask
Set a bit high to enable NMI from that IRQ"</span>]
#[inline(always)]
</span><span class="kw">pub const fn </span>proc0_nmi_mask(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="kw-2">&</span>PROC0_NMI_MASK {
<span class="kw-2">&</span><span class="self">self</span>.proc0_nmi_mask
}
<span class="attr">#[doc = <span class="string">"0x04 - Processor core 1 NMI source mask
Set a bit high to enable NMI from that IRQ"</span>]
#[inline(always)]
</span><span class="kw">pub const fn </span>proc1_nmi_mask(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="kw-2">&</span>PROC1_NMI_MASK {
<span class="kw-2">&</span><span class="self">self</span>.proc1_nmi_mask
}
<span class="attr">#[doc = <span class="string">"0x08 - Configuration for processors"</span>]
#[inline(always)]
</span><span class="kw">pub const fn </span>proc_config(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="kw-2">&</span>PROC_CONFIG {
<span class="kw-2">&</span><span class="self">self</span>.proc_config
}
<span class="attr">#[doc = <span class="string">"0x0c - For each bit, if 1, bypass the input synchronizer between that GPIO
and the GPIO input register in the SIO. The input synchronizers should
generally be unbypassed, to avoid injecting metastabilities into processors.
If you're feeling brave, you can bypass to save two cycles of input
latency. This register applies to GPIO 0...29."</span>]
#[inline(always)]
</span><span class="kw">pub const fn </span>proc_in_sync_bypass(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="kw-2">&</span>PROC_IN_SYNC_BYPASS {
<span class="kw-2">&</span><span class="self">self</span>.proc_in_sync_bypass
}
<span class="attr">#[doc = <span class="string">"0x10 - For each bit, if 1, bypass the input synchronizer between that GPIO
and the GPIO input register in the SIO. The input synchronizers should
generally be unbypassed, to avoid injecting metastabilities into processors.
If you're feeling brave, you can bypass to save two cycles of input
latency. This register applies to GPIO 30...35 (the QSPI IOs)."</span>]
#[inline(always)]
</span><span class="kw">pub const fn </span>proc_in_sync_bypass_hi(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="kw-2">&</span>PROC_IN_SYNC_BYPASS_HI {
<span class="kw-2">&</span><span class="self">self</span>.proc_in_sync_bypass_hi
}
<span class="attr">#[doc = <span class="string">"0x14 - Directly control the SWD debug port of either processor"</span>]
#[inline(always)]
</span><span class="kw">pub const fn </span>dbgforce(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="kw-2">&</span>DBGFORCE {
<span class="kw-2">&</span><span class="self">self</span>.dbgforce
}
<span class="attr">#[doc = <span class="string">"0x18 - Control power downs to memories. Set high to power down memories.
Use with extreme caution"</span>]
#[inline(always)]
</span><span class="kw">pub const fn </span>mempowerdown(<span class="kw-2">&</span><span class="self">self</span>) -> <span class="kw-2">&</span>MEMPOWERDOWN {
<span class="kw-2">&</span><span class="self">self</span>.mempowerdown
}
}
<span class="attr">#[doc = <span class="string">"PROC0_NMI_MASK (rw) register accessor: Processor core 0 NMI source mask
Set a bit high to enable NMI from that IRQ
You can [`read`](crate::generic::Reg::read) this register and get [`proc0_nmi_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_nmi_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
For information about available fields see [`mod@proc0_nmi_mask`]
module"</span>]
</span><span class="kw">pub type </span>PROC0_NMI_MASK = <span class="kw">crate</span>::Reg<proc0_nmi_mask::PROC0_NMI_MASK_SPEC>;
<span class="attr">#[doc = <span class="string">"Processor core 0 NMI source mask
Set a bit high to enable NMI from that IRQ"</span>]
</span><span class="kw">pub mod </span>proc0_nmi_mask;
<span class="attr">#[doc = <span class="string">"PROC1_NMI_MASK (rw) register accessor: Processor core 1 NMI source mask
Set a bit high to enable NMI from that IRQ
You can [`read`](crate::generic::Reg::read) this register and get [`proc1_nmi_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_nmi_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
For information about available fields see [`mod@proc1_nmi_mask`]
module"</span>]
</span><span class="kw">pub type </span>PROC1_NMI_MASK = <span class="kw">crate</span>::Reg<proc1_nmi_mask::PROC1_NMI_MASK_SPEC>;
<span class="attr">#[doc = <span class="string">"Processor core 1 NMI source mask
Set a bit high to enable NMI from that IRQ"</span>]
</span><span class="kw">pub mod </span>proc1_nmi_mask;
<span class="attr">#[doc = <span class="string">"PROC_CONFIG (rw) register accessor: Configuration for processors
You can [`read`](crate::generic::Reg::read) this register and get [`proc_config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
For information about available fields see [`mod@proc_config`]
module"</span>]
</span><span class="kw">pub type </span>PROC_CONFIG = <span class="kw">crate</span>::Reg<proc_config::PROC_CONFIG_SPEC>;
<span class="attr">#[doc = <span class="string">"Configuration for processors"</span>]
</span><span class="kw">pub mod </span>proc_config;
<span class="attr">#[doc = <span class="string">"PROC_IN_SYNC_BYPASS (rw) register accessor: For each bit, if 1, bypass the input synchronizer between that GPIO
and the GPIO input register in the SIO. The input synchronizers should
generally be unbypassed, to avoid injecting metastabilities into processors.
If you're feeling brave, you can bypass to save two cycles of input
latency. This register applies to GPIO 0...29.
You can [`read`](crate::generic::Reg::read) this register and get [`proc_in_sync_bypass::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_in_sync_bypass::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
For information about available fields see [`mod@proc_in_sync_bypass`]
module"</span>]
</span><span class="kw">pub type </span>PROC_IN_SYNC_BYPASS = <span class="kw">crate</span>::Reg<proc_in_sync_bypass::PROC_IN_SYNC_BYPASS_SPEC>;
<span class="attr">#[doc = <span class="string">"For each bit, if 1, bypass the input synchronizer between that GPIO
and the GPIO input register in the SIO. The input synchronizers should
generally be unbypassed, to avoid injecting metastabilities into processors.
If you're feeling brave, you can bypass to save two cycles of input
latency. This register applies to GPIO 0...29."</span>]
</span><span class="kw">pub mod </span>proc_in_sync_bypass;
<span class="attr">#[doc = <span class="string">"PROC_IN_SYNC_BYPASS_HI (rw) register accessor: For each bit, if 1, bypass the input synchronizer between that GPIO
and the GPIO input register in the SIO. The input synchronizers should
generally be unbypassed, to avoid injecting metastabilities into processors.
If you're feeling brave, you can bypass to save two cycles of input
latency. This register applies to GPIO 30...35 (the QSPI IOs).
You can [`read`](crate::generic::Reg::read) this register and get [`proc_in_sync_bypass_hi::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_in_sync_bypass_hi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
For information about available fields see [`mod@proc_in_sync_bypass_hi`]
module"</span>]
</span><span class="kw">pub type </span>PROC_IN_SYNC_BYPASS_HI = <span class="kw">crate</span>::Reg<proc_in_sync_bypass_hi::PROC_IN_SYNC_BYPASS_HI_SPEC>;
<span class="attr">#[doc = <span class="string">"For each bit, if 1, bypass the input synchronizer between that GPIO
and the GPIO input register in the SIO. The input synchronizers should
generally be unbypassed, to avoid injecting metastabilities into processors.
If you're feeling brave, you can bypass to save two cycles of input
latency. This register applies to GPIO 30...35 (the QSPI IOs)."</span>]
</span><span class="kw">pub mod </span>proc_in_sync_bypass_hi;
<span class="attr">#[doc = <span class="string">"DBGFORCE (rw) register accessor: Directly control the SWD debug port of either processor
You can [`read`](crate::generic::Reg::read) this register and get [`dbgforce::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbgforce::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
For information about available fields see [`mod@dbgforce`]
module"</span>]
</span><span class="kw">pub type </span>DBGFORCE = <span class="kw">crate</span>::Reg<dbgforce::DBGFORCE_SPEC>;
<span class="attr">#[doc = <span class="string">"Directly control the SWD debug port of either processor"</span>]
</span><span class="kw">pub mod </span>dbgforce;
<span class="attr">#[doc = <span class="string">"MEMPOWERDOWN (rw) register accessor: Control power downs to memories. Set high to power down memories.
Use with extreme caution
You can [`read`](crate::generic::Reg::read) this register and get [`mempowerdown::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mempowerdown::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
For information about available fields see [`mod@mempowerdown`]
module"</span>]
</span><span class="kw">pub type </span>MEMPOWERDOWN = <span class="kw">crate</span>::Reg<mempowerdown::MEMPOWERDOWN_SPEC>;
<span class="attr">#[doc = <span class="string">"Control power downs to memories. Set high to power down memories.
Use with extreme caution"</span>]
</span><span class="kw">pub mod </span>mempowerdown;
</code></pre></div></section></main></body></html>