The basepri register appears to be aviable on thumbv8m.main but not
thumbv8m.base. At the very least, attempting to compile against a
Cortex-M23 based Microchip ATSAML10E16A generates an error:
```
error[E0432]: unresolved import `cortex_m::register::basepri`
--> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5
|
25 | use cortex_m::register::basepri;
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register`
```
This is an attempt to account for the fact that thumbv8m.base (M23)
MCUs don't have the BASEPRI register but have more than 32
interrupts. This moves away from the architecture specific config
flags and switches to a more functional flag.
Make the mask size depend on the max interrupt id
Rather than assuming a fixed interrupt count of 32 this code uses an
array of u32 bitmasks to calculate the priority mask. The size of this
array is calculated at compile time based on the size of the largest
interrupt id being used in the target code. For thumbv6m this should
be equivalent to the previous version that used a single u32 mask. For
thumbv8m.base it will be larger depending on the interrupts used.
Don't write 0s to the ISER and ICER registers
Writing 0s to these registers is a no-op. Since these masks should be
calculated at compile time, this conditional should result in writes
being optimized out of the code.
Prevent panic on non-arm targets
Panicking on unknown targets was breaking things like the doc build on
linux. This change should only panic when building on unknown arm
targets.
with the upcoming version of heapless we are able to initialize all internal
queues in const context removing the need for late initialization
this commit also removes the "nightly" feature because all the optimization
provided by it are now enabled by default
This commit:
- Implements RFC 147: "all functions must be safe"
- Implements RFC 155: "explicit Context parameter"
- Implements the pending breaking change #141: reject assign syntax in `init`
(which was used to initialize late resources)
- Refactors code generation to make it more readable -- there are no more random
identifiers in the output -- and align it with the book description of RTFM
internals.
- Makes the framework hard depend on `core::mem::MaybeUninit` and thus will
require nightly until that API is stabilized.
- Fixes a ceiling analysis bug where the priority of the system timer was not
considered in the analysis.
- Shrinks the size of all the internal queues by turning `AtomicUsize` indices
into `AtomicU8`s.
- Removes the integration with `owned_singleton`.
