* Update dependencies of stm32g0 timer example
* Replace obsolete probe-run with probe-rs run
* Modify stm32 monotonic to work with timers that have only 2 compare modules
* Add changelog
* Fix typo
* Atomics: Replace polyfill with portable-atomic
* Update Cargo.lock for examples
* RTIC: portable-atomic: Update changelog
* rtic-monotonics: portable-atomic: Update changelog
* lm3s6965: enable critical-section when testing
* xtask: Enable portable-atomic/critical-section
When dealing with rtic-monotonics
* rtic-monotonics: portable-atomics: Do not disable the ability to fallback
---------
Co-authored-by: Emil Fresk <emil.fresk@gmail.com>
* Update Cargo.toml esp32c3 dependency
* fixed esp32c3 example to build with esp32c3=0.22.0 dependency
* added CHANGELOG.md entry for esp32c3 version update
* Rework timer_queue and monotonic architecture
Goals:
* make Monotonic purely internal
* make Monotonic purely tick passed, no fugit involved
* create a wrapper struct in the user's code via a macro that then
converts the "now" from the tick based monotonic to a fugit based
timestamp
We need to proxy the delay functions of the timer queue anyway,
so we could simply perform the conversion in those proxy functions.
* Update cargo.lock
* Update readme of rtic-time
* CI: ESP32: Redact esp_image: Too volatile
* Fixup: Changelog double entry rebase mistake
---------
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
* fix included examples and markdown(book)
fixes: #911
* fix footnote pre_init
* more example link updates
* Restore pool example name
* Example: pool: Upgrade to heapless v0.8
* Example: pool: thumbv6 unsupported: wild cfg-if
Experiment with multi-backend example contained in the example
* Example: lm3s6965: Updated cargo.lock
* Book: Use cargo xtask for by-example
* Docs: Contributing: cargo xtask
---------
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
* Rebase to master
* using interrupt_mod
* bug fixes
* fix other backends
* Add changelog
* forgot about rtic-macros
* backend-specific configuration
* core peripherals optional over macro argument
* pre_init_preprocessing binding
* CI for RISC-V (WIP)
* separation of concerns
* add targets for RISC-V examples
* remove qemu feature
* prepare examples folder
* move examples all together
* move ci out of examples
* minor changes
* add cortex-m
* new xtask: proof of concept
* fix build.yml
* feature typo
* clean rtic examples
* reproduce weird issue
* remove unsafe code in user app
* update dependencies
* allow builds on riscv32imc
* let's fix QEMU
* Update .github/workflows/build.yml
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
* New build.rs
* removing test features
* adapt ui test to new version of clippy
* add more examples to RISC-V backend
* proper configuration of heapless for riscv32imc
* opt-out examples for riscv32imc
* point to new version of riscv-slic
* adapt new macro bindings
* adapt examples and CI to stable
* fix cortex-m CI
* Review
---------
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
The RTIC book mentions Embassy+RTIC but gives no examples.
fmt.
Add feature flag
Seems CI does not deal with 2 levels of depth.
Forgot to stage.
Thumb m arch.
Co-authored-by: Corey Schuhen <cschuhen@gmail.com>
* Fix nrf::timer
* Bootstrap nrf52840-blinky example
* More work on nrf blinky example
* Fix README
* Add asserts for correct timer functionality
* Add correctness check to other monotonics as well
* Update Changelog
* Fix potential timing issues
* Fix race condition in nrf::rtc
* Add changelog
* Add rtc blinky example
* Change rtc example to RC lf clock source
* Add changelog to rtic-time
* Add changelog
* Attempt to fix CI
* Update teensy4-blinky Cargo.lock
