mirror of
https://github.com/rtic-rs/rtic.git
synced 2025-12-18 22:05:37 +01:00
Save, init generation fixed
This commit is contained in:
Emil Fresk
parent
3b4c10e790
commit
ef50aeb2e8
13 changed files with 229 additions and 242 deletions
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@ -3,7 +3,7 @@ use core::{
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sync::atomic::{AtomicBool, Ordering},
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};
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pub use crate::tq::{NotReady, TimerQueue};
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//pub use crate::tq::{NotReady, TimerQueue};
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pub use bare_metal::CriticalSection;
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#[cfg(armv7m)]
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pub use cortex_m::register::basepri;
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68
src/lib.rs
68
src/lib.rs
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@ -32,82 +32,20 @@
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#![deny(missing_docs)]
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#![deny(rust_2018_compatibility)]
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#![deny(rust_2018_idioms)]
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#![deny(warnings)]
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// #![deny(warnings)]
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#![no_std]
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use core::ops::Sub;
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use cortex_m::{
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interrupt::Nr,
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peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, TPIU},
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};
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use cortex_m::{interrupt::Nr, peripheral::NVIC};
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pub use cortex_m_rtic_macros::app;
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pub use rtic_core::{prelude as mutex_prelude, Exclusive, Mutex};
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pub use rtic_core::{prelude as mutex_prelude, Exclusive, monotonic::Monotonic, Mutex};
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#[cfg(armv7m)]
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pub mod cyccnt;
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#[doc(hidden)]
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pub mod export;
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#[doc(hidden)]
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mod tq;
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/// `cortex_m::Peripherals` minus `SYST`
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#[allow(non_snake_case)]
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pub struct Peripherals {
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/// Cache and branch predictor maintenance operations (not present on Cortex-M0 variants)
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pub CBP: CBP,
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/// CPUID
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pub CPUID: CPUID,
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/// Debug Control Block
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pub DCB: DCB,
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/// Data Watchpoint and Trace unit
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pub DWT: DWT,
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/// Flash Patch and Breakpoint unit (not present on Cortex-M0 variants)
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pub FPB: FPB,
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/// Floating Point Unit (only present on `thumbv7em-none-eabihf`)
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pub FPU: FPU,
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/// Instrumentation Trace Macrocell (not present on Cortex-M0 variants)
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pub ITM: ITM,
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/// Memory Protection Unit
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pub MPU: MPU,
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/// Nested Vector Interrupt Controller
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pub NVIC: NVIC,
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/// System Control Block
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pub SCB: SCB,
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// SysTick: System Timer
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// pub SYST: SYST,
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/// Trace Port Interface Unit (not present on Cortex-M0 variants)
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pub TPIU: TPIU,
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}
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impl From<cortex_m::Peripherals> for Peripherals {
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fn from(p: cortex_m::Peripherals) -> Self {
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Self {
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CBP: p.CBP,
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CPUID: p.CPUID,
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DCB: p.DCB,
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DWT: p.DWT,
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FPB: p.FPB,
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FPU: p.FPU,
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ITM: p.ITM,
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MPU: p.MPU,
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NVIC: p.NVIC,
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SCB: p.SCB,
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TPIU: p.TPIU,
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}
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}
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}
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/// Sets the given `interrupt` as pending
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///
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/// This is a convenience function around
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312
src/tq.rs
312
src/tq.rs
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@ -1,156 +1,156 @@
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use core::{
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cmp::{self, Ordering},
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convert::TryInto,
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mem,
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ops::Sub,
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};
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use cortex_m::peripheral::{SCB, SYST};
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use heapless::{binary_heap::Min, ArrayLength, BinaryHeap};
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use crate::Monotonic;
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pub struct TimerQueue<M, T, N>(pub BinaryHeap<NotReady<M, T>, N, Min>)
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where
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M: Monotonic,
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<M::Instant as Sub>::Output: TryInto<u32>,
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N: ArrayLength<NotReady<M, T>>,
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T: Copy;
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impl<M, T, N> TimerQueue<M, T, N>
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where
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M: Monotonic,
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<M::Instant as Sub>::Output: TryInto<u32>,
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N: ArrayLength<NotReady<M, T>>,
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T: Copy,
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{
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/// # Safety
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///
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/// Writing to memory with a transmute in order to enable
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/// interrupts of the SysTick timer
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///
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/// Enqueue a task without checking if it is full
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#[inline]
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pub unsafe fn enqueue_unchecked(&mut self, nr: NotReady<M, T>) {
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let mut is_empty = true;
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// Check if the top contains a non-empty element and if that element is
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// greater than nr
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let if_heap_max_greater_than_nr = self
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.0
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.peek()
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.map(|head| {
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is_empty = false;
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nr.instant < head.instant
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})
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.unwrap_or(true);
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if if_heap_max_greater_than_nr {
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if is_empty {
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mem::transmute::<_, SYST>(()).enable_interrupt();
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}
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// Set SysTick pending
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SCB::set_pendst();
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}
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self.0.push_unchecked(nr);
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}
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/// Dequeue a task from the TimerQueue
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#[inline]
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pub fn dequeue(&mut self) -> Option<(T, u8)> {
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unsafe {
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if let Some(instant) = self.0.peek().map(|p| p.instant) {
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let now = M::now();
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if instant < now {
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// task became ready
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let nr = self.0.pop_unchecked();
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Some((nr.task, nr.index))
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} else {
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// set a new timeout
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const MAX: u32 = 0x00ffffff;
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let ratio = M::ratio();
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let dur = match (instant - now).try_into().ok().and_then(|x| {
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x.checked_mul(ratio.numerator)
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.map(|x| x / ratio.denominator)
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}) {
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None => MAX,
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// ARM Architecture Reference Manual says:
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// "Setting SYST_RVR to zero has the effect of
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// disabling the SysTick counter independently
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// of the counter enable bit."
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Some(0) => 1,
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Some(x) => cmp::min(MAX, x),
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};
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mem::transmute::<_, SYST>(()).set_reload(dur);
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// Start counting down from the new reload
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mem::transmute::<_, SYST>(()).clear_current();
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None
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}
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} else {
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// The queue is empty
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mem::transmute::<_, SYST>(()).disable_interrupt();
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None
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}
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}
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}
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}
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pub struct NotReady<M, T>
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where
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T: Copy,
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M: Monotonic,
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<M::Instant as Sub>::Output: TryInto<u32>,
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{
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pub index: u8,
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pub instant: M::Instant,
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pub task: T,
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}
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impl<M, T> Eq for NotReady<M, T>
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where
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T: Copy,
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M: Monotonic,
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<M::Instant as Sub>::Output: TryInto<u32>,
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{
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}
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impl<M, T> Ord for NotReady<M, T>
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where
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T: Copy,
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M: Monotonic,
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<M::Instant as Sub>::Output: TryInto<u32>,
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{
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fn cmp(&self, other: &Self) -> Ordering {
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self.instant.cmp(&other.instant)
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}
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}
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impl<M, T> PartialEq for NotReady<M, T>
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where
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T: Copy,
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M: Monotonic,
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<M::Instant as Sub>::Output: TryInto<u32>,
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{
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fn eq(&self, other: &Self) -> bool {
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self.instant == other.instant
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}
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}
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impl<M, T> PartialOrd for NotReady<M, T>
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where
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T: Copy,
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M: Monotonic,
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<M::Instant as Sub>::Output: TryInto<u32>,
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{
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fn partial_cmp(&self, other: &Self) -> Option<Ordering> {
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Some(self.cmp(&other))
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}
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}
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// use core::{
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// cmp::{self, Ordering},
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// convert::TryInto,
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// mem,
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// ops::Sub,
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// };
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//
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// use cortex_m::peripheral::{SCB, SYST};
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// use heapless::{binary_heap::Min, ArrayLength, BinaryHeap};
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//
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// use crate::Monotonic;
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//
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// pub struct TimerQueue<M, T, N>(pub BinaryHeap<NotReady<M, T>, N, Min>)
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// where
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// M: Monotonic,
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// <M::Instant as Sub>::Output: TryInto<u32>,
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// N: ArrayLength<NotReady<M, T>>,
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// T: Copy;
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//
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// impl<M, T, N> TimerQueue<M, T, N>
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// where
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// M: Monotonic,
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// <M::Instant as Sub>::Output: TryInto<u32>,
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// N: ArrayLength<NotReady<M, T>>,
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// T: Copy,
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// {
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// /// # Safety
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// ///
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// /// Writing to memory with a transmute in order to enable
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// /// interrupts of the SysTick timer
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// ///
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// /// Enqueue a task without checking if it is full
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// #[inline]
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// pub unsafe fn enqueue_unchecked(&mut self, nr: NotReady<M, T>) {
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// let mut is_empty = true;
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// // Check if the top contains a non-empty element and if that element is
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// // greater than nr
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// let if_heap_max_greater_than_nr = self
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// .0
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// .peek()
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// .map(|head| {
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// is_empty = false;
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// nr.instant < head.instant
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// })
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// .unwrap_or(true);
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// if if_heap_max_greater_than_nr {
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// if is_empty {
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// mem::transmute::<_, SYST>(()).enable_interrupt();
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// }
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//
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// // Set SysTick pending
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// SCB::set_pendst();
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// }
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//
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// self.0.push_unchecked(nr);
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// }
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//
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// /// Dequeue a task from the TimerQueue
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// #[inline]
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// pub fn dequeue(&mut self) -> Option<(T, u8)> {
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// unsafe {
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// if let Some(instant) = self.0.peek().map(|p| p.instant) {
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// let now = M::now();
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//
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// if instant < now {
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// // task became ready
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// let nr = self.0.pop_unchecked();
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//
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// Some((nr.task, nr.index))
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// } else {
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// // set a new timeout
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// const MAX: u32 = 0x00ffffff;
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//
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// let ratio = M::ratio();
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// let dur = match (instant - now).try_into().ok().and_then(|x| {
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// x.checked_mul(ratio.numerator)
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// .map(|x| x / ratio.denominator)
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// }) {
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// None => MAX,
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//
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// // ARM Architecture Reference Manual says:
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// // "Setting SYST_RVR to zero has the effect of
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// // disabling the SysTick counter independently
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// // of the counter enable bit."
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// Some(0) => 1,
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//
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// Some(x) => cmp::min(MAX, x),
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// };
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// mem::transmute::<_, SYST>(()).set_reload(dur);
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//
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// // Start counting down from the new reload
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// mem::transmute::<_, SYST>(()).clear_current();
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//
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// None
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// }
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// } else {
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// // The queue is empty
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// mem::transmute::<_, SYST>(()).disable_interrupt();
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//
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// None
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// }
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// }
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// }
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// }
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//
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// pub struct NotReady<M, T>
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// where
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// T: Copy,
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// M: Monotonic,
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// <M::Instant as Sub>::Output: TryInto<u32>,
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// {
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// pub index: u8,
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// pub instant: M::Instant,
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// pub task: T,
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// }
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//
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// impl<M, T> Eq for NotReady<M, T>
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// where
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// T: Copy,
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// M: Monotonic,
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// <M::Instant as Sub>::Output: TryInto<u32>,
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// {
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// }
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//
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// impl<M, T> Ord for NotReady<M, T>
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// where
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// T: Copy,
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// M: Monotonic,
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// <M::Instant as Sub>::Output: TryInto<u32>,
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// {
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// fn cmp(&self, other: &Self) -> Ordering {
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// self.instant.cmp(&other.instant)
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// }
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// }
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//
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// impl<M, T> PartialEq for NotReady<M, T>
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// where
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// T: Copy,
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// M: Monotonic,
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// <M::Instant as Sub>::Output: TryInto<u32>,
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// {
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// fn eq(&self, other: &Self) -> bool {
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// self.instant == other.instant
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// }
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// }
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//
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// impl<M, T> PartialOrd for NotReady<M, T>
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// where
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// T: Copy,
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// M: Monotonic,
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// <M::Instant as Sub>::Output: TryInto<u32>,
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// {
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// fn partial_cmp(&self, other: &Self) -> Option<Ordering> {
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// Some(self.cmp(&other))
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// }
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// }
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