mirror/rtic
1
0
Fork 0
mirror of https://github.com/rtic-rs/rtic.git synced 2024-11-23 20:22:51 +01:00
Code Issues Projects Releases Packages Wiki Activity

Enable the DWT unit before poking at its registers.

Browse source 
On cold boot, the DWT unit is off, which means our attempts to clear and
disable the cycle counter in pre-init don't work. This seems to result
in access to CYCCNT always returning 1073741824, which delays tasks
scheduled in init by that many cycles (~15s at 72 MHz).

Fixes #196.
This commit is contained in:
Josh Gao 2019-07-26 03:15:13 -07:00
parent eca12fecef
commit ec1d508040
1 changed files with 2 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
macros/src/codegen.rs
View file

@ -507,7 +507,6 @@ fn post_init(ctxt: &Context, app: &App, analysis: &Analysis) -> proc_macro2::Tok
// Enable cycle counter
if cfg!(feature = "timer-queue") {
exprs.push(quote!(p.DCB.enable_trace()));
exprs.push(quote!(p.DWT.enable_cycle_counter()));
}
@ -2024,6 +2023,8 @@ fn pre_init(ctxt: &Context, app: &App, analysis: &Analysis) -> proc_macro2::Toke
// Set the cycle count to 0 and disable it while `init` executes
if cfg!(feature = "timer-queue") {
// We need to explicitly enable the trace block to set CYCCNT.
exprs.push(quote!(p.DCB.enable_trace();));
exprs.push(quote!(p.DWT.ctrl.modify(|r| r & !1);));
exprs.push(quote!(p.DWT.cyccnt.write(0);));
}