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bump esp32-c3

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This commit is contained in:
MikeGstefan 2024-11-14 20:16:57 -05:00
parent d251ba7173
commit e4d991d4d9
3 changed files with 6 additions and 6 deletions
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2
rtic-monotonics/Cargo.toml
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@ -67,7 +67,7 @@ stm32-metapac = { version = "15.0.0", optional = true }
imxrt-ral = { version = "0.5.3", optional = true }
esp32c3 = {version = "0.25.0", optional = true }
esp32c3 = {version = "0.26.0", optional = true }
riscv = {version = "0.12.1", optional = true }

2
rtic/Cargo.toml
View file

@ -26,7 +26,7 @@ name = "rtic"
[dependencies]
riscv-slic = { version = "0.1.1", optional = true }
esp32c3 = { version = "0.25.0", optional = true }
esp32c3 = { version = "0.26.0", optional = true }
riscv = { version = "0.12.1", optional = true }
cortex-m = { version = "0.7.0", optional = true }
bare-metal = "1.0.0"

8
rtic/src/export/riscv_esp32c3.rs
View file

@ -71,13 +71,13 @@ pub unsafe fn lock<T, R>(ptr: *mut T, ceiling: u8, f: impl FnOnce(&mut T) -> R)
unsafe {
(*INTERRUPT_CORE0::ptr())
.cpu_int_thresh()
.write(|w| w.cpu_int_thresh().bits(ceiling + 1))
.write(|w| w.cpu_int_thresh().bits(ceiling + 1));
} //esp32c3 lets interrupts with prio equal to threshold through so we up it by one
let r = f(&mut *ptr);
unsafe {
(*INTERRUPT_CORE0::ptr())
.cpu_int_thresh()
.write(|w| w.cpu_int_thresh().bits(current))
.write(|w| w.cpu_int_thresh().bits(current));
}
r
}
@ -106,7 +106,7 @@ pub fn pend(int: Interrupt) {
.cpu_intr_from_cpu_3()
.write(|w| w.cpu_intr_from_cpu_3().bit(true)),
_ => panic!("Unsupported software interrupt"), //should never happen, checked at compile time
}
};
}
}
@ -132,7 +132,7 @@ pub fn unpend(int: Interrupt) {
.cpu_intr_from_cpu_3()
.write(|w| w.cpu_intr_from_cpu_3().bit(false)),
_ => panic!("Unsupported software interrupt"),
}
};
}
}