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atsamd21: unmask TC4 interrupt
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parent
03ace97cd1
commit
d71ef67c4c
3 changed files with 7 additions and 9 deletions
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@ -118,7 +118,7 @@ imxrt_gpt2 = ["imxrt"]
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esp32c3-systimer = ["dep:esp32c3", "dep:riscv"]
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esp32c3-systimer = ["dep:esp32c3", "dep:riscv"]
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# ATSAMD21 Timer
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# ATSAMD21 Timer
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atsamd21g = ["dep:atsamd21g"]
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atsamd21g = ["dep:cortex-m", "dep:atsamd21g"]
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# STM32 timers
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# STM32 timers
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@ -25,14 +25,6 @@
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//! Mono::delay(100.millis()).await;
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//! Mono::delay(100.millis()).await;
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//! }
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//! }
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//! }
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//! }
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//!
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//! // FIXME: the interrupt handler is not working, but re-implementing it in a RTIC task does
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//! // Comment the interrupt handler `unsafe extern "C" fn TC4()` and add the following RTIC task
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//! #[task(binds = TC4)]
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//! fn tc4(_cx: tc4::Context) {
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//! use rtic_time::timer_queue::TimerQueueBackend;
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//! unsafe { Tc4Tc5Backend::timer_queue().on_monotonic_interrupt() };
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//! }
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//! ```
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//! ```
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/// Common definitions and traits for using the ATSAMD21 TC4/5 monotonic
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/// Common definitions and traits for using the ATSAMD21 TC4/5 monotonic
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@ -114,6 +106,11 @@ impl Tc4Tc5Backend {
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// Enable the timer
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// Enable the timer
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tc4.ctrla().modify(|_, w| w.enable().set_bit());
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tc4.ctrla().modify(|_, w| w.enable().set_bit());
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Self::sync();
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Self::sync();
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unsafe {
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crate::set_monotonic_prio(pac::NVIC_PRIO_BITS, pac::Interrupt::TC4);
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pac::NVIC::unmask(pac::Interrupt::TC4);
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}
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}
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}
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}
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}
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@ -99,6 +99,7 @@ pub(crate) const fn cortex_logical2hw(logical: u8, nvic_prio_bits: u8) -> u8 {
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feature = "nrf5340-net",
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feature = "nrf5340-net",
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feature = "nrf9160",
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feature = "nrf9160",
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feature = "imxrt",
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feature = "imxrt",
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feature = "atsamd21g",
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stm32,
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stm32,
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))]
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))]
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pub(crate) unsafe fn set_monotonic_prio(
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pub(crate) unsafe fn set_monotonic_prio(
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