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Require exclusive access to the RESET peripheral for RP2040/RP2350

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If you don't have exclusive access to the RESET peripheral, someone else
could race you on the read/modify/write cycle on the update of the
RESETS.reset register.

This is a breaking change.
This commit is contained in:
Jonathan 'theJPster' Pallant 2025-06-15 13:36:11 +01:00
parent a2dfb62ffc
commit c04b02e7c9
No known key found for this signature in database
2 changed files with 2 additions and 2 deletions
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2
rtic-monotonics/src/rp2040.rs
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@ -50,7 +50,7 @@ impl TimerBackend {
/// **Do not use this function directly.** /// **Do not use this function directly.**
/// ///
/// Use the prelude macros instead. /// Use the prelude macros instead.
pub fn _start(timer: TIMER, resets: &RESETS) { pub fn _start(timer: TIMER, resets: &mut RESETS) {
resets.reset().modify(|_, w| w.timer().clear_bit()); resets.reset().modify(|_, w| w.timer().clear_bit());
while resets.reset_done().read().timer().bit_is_clear() {} while resets.reset_done().read().timer().bit_is_clear() {}
timer.inte().modify(|_, w| w.alarm_0().bit(true)); timer.inte().modify(|_, w| w.alarm_0().bit(true));

2
rtic-monotonics/src/rp235x.rs
View file

@ -52,7 +52,7 @@ impl TimerBackend {
/// **Do not use this function directly.** /// **Do not use this function directly.**
/// ///
/// Use the prelude macros instead. /// Use the prelude macros instead.
pub fn _start(timer: TIMER0, resets: &RESETS) { pub fn _start(timer: TIMER0, resets: &mut RESETS) {
resets.reset().modify(|_, w| w.timer0().clear_bit()); resets.reset().modify(|_, w| w.timer0().clear_bit());
while resets.reset_done().read().timer0().bit_is_clear() {} while resets.reset_done().read().timer0().bit_is_clear() {}
timer.inte().modify(|_, w| w.alarm_0().bit(true)); timer.inte().modify(|_, w| w.alarm_0().bit(true));