mirror of
https://github.com/rtic-rs/rtic.git
synced 2025-12-19 06:15:45 +01:00
Added esp32c6 support and example
This commit is contained in:
parent
5a8ff70f85
commit
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17 changed files with 1526 additions and 2 deletions
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@ -3,6 +3,7 @@
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feature = "cortex-m-basepri",
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feature = "test-template",
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feature = "riscv-esp32c3",
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feature = "riscv-esp32c6",
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feature = "riscv-slic",
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)))]
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compile_error!("No backend selected");
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@ -25,6 +26,12 @@ pub use esp32c3::*;
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#[cfg(feature = "riscv-esp32c3")]
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mod esp32c3;
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#[cfg(feature = "riscv-esp32c6")]
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pub use esp32c6::*;
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#[cfg(feature = "riscv-esp32c6")]
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mod esp32c6;
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#[cfg(feature = "riscv-slic")]
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pub use riscv_slic::*;
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249
rtic-macros/src/codegen/bindings/esp32c6.rs
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249
rtic-macros/src/codegen/bindings/esp32c6.rs
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@ -0,0 +1,249 @@
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#[cfg(feature = "riscv-esp32c6")]
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pub use esp32c6::*;
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#[cfg(feature = "riscv-esp32c6")]
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mod esp32c6 {
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use crate::{
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analyze::Analysis as CodegenAnalysis,
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codegen::util,
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syntax::{analyze::Analysis as SyntaxAnalysis, ast::App},
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};
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use proc_macro2::{Span, TokenStream as TokenStream2};
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use quote::quote;
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use std::collections::HashSet;
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use syn::{parse, Attribute, Ident};
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#[allow(clippy::too_many_arguments)]
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pub fn impl_mutex(
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_app: &App,
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_analysis: &CodegenAnalysis,
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cfgs: &[Attribute],
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resources_prefix: bool,
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name: &Ident,
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ty: &TokenStream2,
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ceiling: u8,
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ptr: &TokenStream2,
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) -> TokenStream2 {
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let path = if resources_prefix {
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quote!(shared_resources::#name)
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} else {
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quote!(#name)
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};
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quote!(
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#(#cfgs)*
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impl<'a> rtic::Mutex for #path<'a> {
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type T = #ty;
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#[inline(always)]
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fn lock<RTIC_INTERNAL_R>(&mut self, f: impl FnOnce(&mut #ty) -> RTIC_INTERNAL_R) -> RTIC_INTERNAL_R {
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/// Priority ceiling
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const CEILING: u8 = #ceiling;
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unsafe {
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rtic::export::lock(
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#ptr,
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CEILING,
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f,
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)
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}
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}
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}
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)
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}
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pub fn interrupt_ident() -> Ident {
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let span = Span::call_site();
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Ident::new("Interrupt", span)
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}
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pub fn interrupt_mod(app: &App) -> TokenStream2 {
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let device = &app.args.device;
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let interrupt = interrupt_ident();
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quote!(#device::#interrupt)
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}
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pub fn extra_assertions(_: &App, _: &SyntaxAnalysis) -> Vec<TokenStream2> {
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vec![]
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}
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pub fn pre_init_preprocessing(_app: &mut App, _analysis: &SyntaxAnalysis) -> parse::Result<()> {
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Ok(())
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}
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pub fn pre_init_checks(app: &App, _: &SyntaxAnalysis) -> Vec<TokenStream2> {
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let mut stmts = vec![];
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// check that all dispatchers exists in the `Interrupt` enumeration regardless of whether
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// they are used or not
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let rt_err = util::rt_err_ident();
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for name in app.args.dispatchers.keys() {
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stmts.push(quote!(let _ = #rt_err::Interrupt::#name;));
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}
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stmts
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}
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pub fn pre_init_enable_interrupts(app: &App, analysis: &CodegenAnalysis) -> Vec<TokenStream2> {
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let mut stmts = vec![];
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let mut curr_cpu_id: u8 = 1; //cpu interrupt id 0 is reserved
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let rt_err = util::rt_err_ident();
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let max_prio: usize = 15; //unfortunately this is not part of pac, but we know that max prio is 15.
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let interrupt_ids = analysis.interrupts.iter().map(|(p, (id, _))| (p, id));
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// Unmask interrupts and set their priorities
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for (&priority, name) in interrupt_ids.chain(
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app.hardware_tasks
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.values()
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.filter_map(|task| Some((&task.args.priority, &task.args.binds))),
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) {
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let es = format!(
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"Maximum priority used by interrupt vector '{name}' is more than supported by hardware"
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);
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// Compile time assert that this priority is supported by the device
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stmts.push(quote!(
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const _: () = if (#max_prio) <= #priority as usize { ::core::panic!(#es); };
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));
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stmts.push(quote!(
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rtic::export::enable(
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#rt_err::Interrupt::#name,
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#priority,
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#curr_cpu_id,
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);
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));
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curr_cpu_id += 1;
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}
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stmts
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}
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pub fn architecture_specific_analysis(
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app: &App,
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_analysis: &SyntaxAnalysis,
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) -> parse::Result<()> {
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//check if the dispatchers are supported
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for name in app.args.dispatchers.keys() {
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let name_s = name.to_string();
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match &*name_s {
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"FROM_CPU_INTR0" | "FROM_CPU_INTR1" | "FROM_CPU_INTR2" | "FROM_CPU_INTR3" => {}
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_ => {
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return Err(parse::Error::new(
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name.span(),
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"Only FROM_CPU_INTRX are supported as dispatchers",
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));
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}
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}
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}
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// Check that there are enough external interrupts to dispatch the software tasks and the timer
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// queue handler
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let mut first = None;
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let priorities = app
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.software_tasks
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.iter()
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.map(|(name, task)| {
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first = Some(name);
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task.args.priority
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})
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.filter(|prio| *prio > 0)
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.collect::<HashSet<_>>();
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let need = priorities.len();
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let given = app.args.dispatchers.len();
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if need > given {
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let s = {
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format!(
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"not enough interrupts to dispatch \
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all software tasks (need: {need}; given: {given})"
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)
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};
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// If not enough tasks and first still is None, may cause
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// "custom attribute panicked" due to unwrap on None
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return Err(parse::Error::new(first.unwrap().span(), s));
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}
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Ok(())
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}
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pub fn interrupt_entry(_app: &App, _analysis: &CodegenAnalysis) -> Vec<TokenStream2> {
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vec![]
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}
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pub fn interrupt_exit(_app: &App, _analysis: &CodegenAnalysis) -> Vec<TokenStream2> {
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vec![]
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}
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pub fn check_stack_overflow_before_init(
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_app: &App,
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_analysis: &CodegenAnalysis,
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) -> Vec<TokenStream2> {
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vec![quote!(
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// Check for stack overflow using symbols from `risc-v-rt`.
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extern "C" {
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pub static _stack_start: u32;
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pub static _bss_end: u32;
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}
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let stack_start = &_stack_start as *const _ as u32;
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let ebss = &_bss_end as *const _ as u32;
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if stack_start > ebss {
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// No flip-link usage, check the SP for overflow.
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if rtic::export::read_sp() <= ebss {
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panic!("Stack overflow after allocating executors");
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}
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}
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)]
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}
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pub fn async_entry(
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_app: &App,
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_analysis: &CodegenAnalysis,
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dispatcher_name: Ident,
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) -> Vec<TokenStream2> {
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let mut stmts = vec![];
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stmts.push(quote!(
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rtic::export::unpend(rtic::export::Interrupt::#dispatcher_name); //simulate cortex-m behavior by unpending the interrupt on entry.
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));
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stmts
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}
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pub fn async_prio_limit(app: &App, analysis: &CodegenAnalysis) -> Vec<TokenStream2> {
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let max = if let Some(max) = analysis.max_async_prio {
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quote!(#max)
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} else {
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// No limit
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let device = &app.args.device;
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quote!(1 << #device::NVIC_PRIO_BITS)
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};
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vec![quote!(
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/// Holds the maximum priority level for use by async HAL drivers.
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#[no_mangle]
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static RTIC_ASYNC_MAX_LOGICAL_PRIO: u8 = #max;
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)]
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}
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pub fn handler_config(
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app: &App,
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analysis: &CodegenAnalysis,
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dispatcher_name: Ident,
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) -> Vec<TokenStream2> {
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let mut stmts = vec![];
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let mut curr_cpu_id = 1;
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//let mut ret = "";
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let interrupt_ids = analysis.interrupts.iter().map(|(p, (id, _))| (p, id));
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for (_, name) in interrupt_ids.chain(
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app.hardware_tasks
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.values()
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.filter_map(|task| Some((&task.args.priority, &task.args.binds))),
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) {
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if *name == dispatcher_name {
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let ret = &("cpu_int_".to_owned() + &curr_cpu_id.to_string() + "_handler");
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stmts.push(quote!(#[export_name = #ret]));
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}
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curr_cpu_id += 1;
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}
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stmts
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}
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pub fn extra_modules(_app: &App, _analysis: &SyntaxAnalysis) -> Vec<TokenStream2> {
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vec![]
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}
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}
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@ -15,6 +15,7 @@ macro_rules! with_backend {
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feature = "cortex-m-basepri",
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feature = "test-template",
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feature = "riscv-esp32c3",
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feature = "riscv-esp32c6",
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feature = "riscv-slic",
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))]
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$($tokens)*
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@ -118,6 +119,7 @@ with_backend! {
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feature = "cortex-m-basepri",
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feature = "test-template",
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feature = "riscv-esp32c3",
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feature = "riscv-esp32c6",
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feature = "riscv-slic",
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)))]
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compile_error!("Cannot compile. No backend feature selected.");
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@ -3,6 +3,7 @@
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feature = "cortex-m-basepri",
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feature = "test-template",
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feature = "riscv-esp32c3",
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feature = "riscv-esp32c6",
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feature = "riscv-slic",
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)))]
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compile_error!("No backend selected");
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@ -16,6 +17,9 @@ pub use template::*;
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#[cfg(feature = "riscv-esp32c3")]
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pub use esp32c3::*;
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#[cfg(feature = "riscv-esp32c6")]
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pub use esp32c6::*;
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#[cfg(feature = "riscv-slic")]
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pub use riscv_slic::*;
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@ -28,5 +32,8 @@ mod template;
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#[cfg(feature = "riscv-esp32c3")]
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mod esp32c3;
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#[cfg(feature = "riscv-esp32c6")]
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mod esp32c6;
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#[cfg(feature = "riscv-slic")]
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mod riscv_slic;
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16
rtic-macros/src/syntax/backend/esp32c6.rs
Normal file
16
rtic-macros/src/syntax/backend/esp32c6.rs
Normal file
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@ -0,0 +1,16 @@
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use syn::{
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parse::{Parse, ParseStream},
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Error, Result,
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};
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#[derive(Debug)]
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pub struct BackendArgs();
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impl Parse for BackendArgs {
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fn parse(input: ParseStream) -> Result<Self> {
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Err(Error::new(
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input.span(),
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"esp32c6 backend does not accept any arguments",
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))
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}
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}
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