add homogeneous multi-core support

homogeneous/Cargo.toml

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+[package]
+authors = ["Jorge Aparicio <jorge@japaric.io>"]
+edition = "2018"
+name = "homogeneous"
+# this crate is only used for testing
+publish = false
+version = "0.0.0-alpha.0"
+
+[dependencies]
+bare-metal = "0.2.4"
+
+[dependencies.cortex-m-rtfm]
+path = ".."
+features = ["homogeneous"]
+
+[dev-dependencies]
+panic-halt = "0.2.0"

homogeneous/README.md

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+This directory contains *homogeneous* multi-core compile pass tests.

homogeneous/examples/smallest.rs

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+#![no_main]
+#![no_std]
+
+use panic_halt as _;
+
+#[rtfm::app(cores = 2, device = homogeneous)]
+const APP: () = {};

homogeneous/examples/x-init-2.rs

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+//! [compile-pass] Cross initialization of late resources
+
+#![deny(unsafe_code)]
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+use panic_halt as _;
+
+#[rtfm::app(cores = 2, device = homogeneous)]
+const APP: () = {
+    extern "C" {
+        // owned by core #1 but initialized by core #0
+        static mut X: u32;
+
+        // owned by core #0 but initialized by core #1
+        static mut Y: u32;
+    }
+
+    #[init(core = 0, late = [X])]
+    fn a(_: a::Context) -> a::LateResources {
+        a::LateResources { X: 0 }
+    }
+
+    #[idle(core = 0, resources = [Y])]
+    fn b(_: b::Context) -> ! {
+        loop {}
+    }
+
+    #[init(core = 1)]
+    fn c(_: c::Context) -> c::LateResources {
+        c::LateResources { Y: 0 }
+    }
+
+    #[idle(core = 1, resources = [X])]
+    fn d(_: d::Context) -> ! {
+        loop {}
+    }
+};

homogeneous/examples/x-init.rs

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+//! [compile-pass] Split initialization of late resources
+
+#![deny(unsafe_code)]
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+use panic_halt as _;
+
+#[rtfm::app(cores = 2, device = homogeneous)]
+const APP: () = {
+    extern "C" {
+        static mut X: u32;
+        static mut Y: u32;
+    }
+
+    #[init(core = 0, late = [X])]
+    fn a(_: a::Context) -> a::LateResources {
+        a::LateResources { X: 0 }
+    }
+
+    #[init(core = 1)]
+    fn b(_: b::Context) -> b::LateResources {
+        b::LateResources { Y: 0 }
+    }
+};

homogeneous/examples/x-schedule.rs

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+#![no_main]
+#![no_std]
+
+use panic_halt as _;
+
+#[rtfm::app(cores = 2, device = homogeneous, monotonic = homogeneous::MT)]
+const APP: () = {
+    #[init(core = 0, spawn = [ping])]
+    fn init(c: init::Context) {
+        c.spawn.ping().ok();
+    }
+
+    #[task(core = 0, schedule = [ping])]
+    fn pong(c: pong::Context) {
+        c.schedule.ping(c.scheduled + 1_000_000).ok();
+    }
+
+    #[task(core = 1, schedule = [pong])]
+    fn ping(c: ping::Context) {
+        c.schedule.pong(c.scheduled + 1_000_000).ok();
+    }
+
+    extern "C" {
+        #[core = 0]
+        fn I0();
+
+        #[core = 0]
+        fn I1();
+
+        #[core = 1]
+        fn I0();
+
+        #[core = 1]
+        fn I1();
+    }
+};

homogeneous/examples/x-spawn.rs

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+#![no_main]
+#![no_std]
+
+use panic_halt as _;
+
+#[rtfm::app(cores = 2, device = homogeneous)]
+const APP: () = {
+    #[init(core = 0, spawn = [foo])]
+    fn init(c: init::Context) {
+        c.spawn.foo().ok();
+    }
+
+    #[task(core = 1)]
+    fn foo(_: foo::Context) {}
+
+    extern "C" {
+        #[core = 1]
+        fn I0();
+    }
+};

homogeneous/src/lib.rs

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+//! Fake multi-core PAC
+
+#![no_std]
+
+use core::{
+    cmp::Ordering,
+    ops::{Add, Sub},
+};
+
+use bare_metal::Nr;
+use rtfm::Monotonic;
+
+// both cores have the exact same interrupts
+pub use Interrupt_0 as Interrupt_1;
+
+// Fake priority bits
+pub const NVIC_PRIO_BITS: u8 = 3;
+
+pub fn xpend(_core: u8, _interrupt: impl Nr) {}
+
+/// Fake monotonic timer
+pub struct MT;
+
+unsafe impl Monotonic for MT {
+    type Instant = Instant;
+
+    fn ratio() -> u32 {
+        1
+    }
+
+    unsafe fn reset() {
+        (0xE0001004 as *mut u32).write_volatile(0)
+    }
+
+    fn now() -> Instant {
+        unsafe { Instant((0xE0001004 as *const u32).read_volatile() as i32) }
+    }
+
+    fn zero() -> Instant {
+        Instant(0)
+    }
+}
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Instant(i32);
+
+impl Add<u32> for Instant {
+    type Output = Instant;
+
+    fn add(self, rhs: u32) -> Self {
+        Instant(self.0.wrapping_add(rhs as i32))
+    }
+}
+
+impl Sub for Instant {
+    type Output = u32;
+
+    fn sub(self, rhs: Self) -> u32 {
+        self.0.checked_sub(rhs.0).unwrap() as u32
+    }
+}
+
+impl Ord for Instant {
+    fn cmp(&self, rhs: &Self) -> Ordering {
+        self.0.wrapping_sub(rhs.0).cmp(&0)
+    }
+}
+
+impl PartialOrd for Instant {
+    fn partial_cmp(&self, rhs: &Self) -> Option<Ordering> {
+        Some(self.cmp(rhs))
+    }
+}
+
+// Fake interrupts
+#[allow(non_camel_case_types)]
+#[derive(Clone, Copy)]
+#[repr(u8)]
+pub enum Interrupt_0 {
+    I0 = 0,
+    I1 = 1,
+    I2 = 2,
+    I3 = 3,
+    I4 = 4,
+    I5 = 5,
+    I6 = 6,
+    I7 = 7,
+}
+
+unsafe impl Nr for Interrupt_0 {
+    fn nr(&self) -> u8 {
+        *self as u8
+    }
+}