diff --git a/rtic-monotonics/Cargo.toml b/rtic-monotonics/Cargo.toml
index c644ce7f59..c4396ad244 100644
--- a/rtic-monotonics/Cargo.toml
+++ b/rtic-monotonics/Cargo.toml
@@ -69,4 +69,1348 @@ nrf5340-net = ["dep:cortex-m", "dep:nrf5340-net-pac", "dep:critical-section"]
 nrf9160 = ["dep:cortex-m", "dep:nrf9160-pac", "dep:critical-section"]
 
 # STM32 timers
+# Use as `features = ["stm32g081kb", "stm32_tim15"]`
+stm32_tim2 = []
+stm32_tim3 = []
+stm32_tim4 = []
+stm32_tim5 = []
+stm32_tim12 = []
+stm32_tim15 = []
+
+# Maintainers: this `stm32-metapac` feature list is taken from:
+# https://github.com/embassy-rs/embassy/blob/2e6f4237f2410aa18c9866a5a1a5ed1f3bec8a4e/embassy-stm32/Cargo.toml#L143
+# It should be updated if `stm32-metapac` version changes because it might contain new chip definitions.
+stm32l100c6-a = ["dep:cortex-m", "stm32-metapac/stm32l100c6-a"]
+stm32l100r8-a = ["dep:cortex-m", "stm32-metapac/stm32l100r8-a"]
+stm32l100rb-a = ["dep:cortex-m", "stm32-metapac/stm32l100rb-a"]
+stm32l151c6-a = ["dep:cortex-m", "stm32-metapac/stm32l151c6-a"]
+stm32l151c8-a = ["dep:cortex-m", "stm32-metapac/stm32l151c8-a"]
+stm32l151cb-a = ["dep:cortex-m", "stm32-metapac/stm32l151cb-a"]
+stm32l151r6-a = ["dep:cortex-m", "stm32-metapac/stm32l151r6-a"]
+stm32l151r8-a = ["dep:cortex-m", "stm32-metapac/stm32l151r8-a"]
+stm32l151rb-a = ["dep:cortex-m", "stm32-metapac/stm32l151rb-a"]
+stm32l151rc-a = ["dep:cortex-m", "stm32-metapac/stm32l151rc-a"]
+stm32l151v8-a = ["dep:cortex-m", "stm32-metapac/stm32l151v8-a"]
+stm32l151vb-a = ["dep:cortex-m", "stm32-metapac/stm32l151vb-a"]
+stm32l151vc-a = ["dep:cortex-m", "stm32-metapac/stm32l151vc-a"]
+stm32l151vd-x = ["dep:cortex-m", "stm32-metapac/stm32l151vd-x"]
+stm32l152c6-a = ["dep:cortex-m", "stm32-metapac/stm32l152c6-a"]
+stm32l152c8-a = ["dep:cortex-m", "stm32-metapac/stm32l152c8-a"]
+stm32l152cb-a = ["dep:cortex-m", "stm32-metapac/stm32l152cb-a"]
+stm32l152r6-a = ["dep:cortex-m", "stm32-metapac/stm32l152r6-a"]
+stm32l152r8-a = ["dep:cortex-m", "stm32-metapac/stm32l152r8-a"]
+stm32l152rb-a = ["dep:cortex-m", "stm32-metapac/stm32l152rb-a"]
+stm32l152rc-a = ["dep:cortex-m", "stm32-metapac/stm32l152rc-a"]
+stm32l152v8-a = ["dep:cortex-m", "stm32-metapac/stm32l152v8-a"]
+stm32l152vb-a = ["dep:cortex-m", "stm32-metapac/stm32l152vb-a"]
+stm32l152vc-a = ["dep:cortex-m", "stm32-metapac/stm32l152vc-a"]
+stm32l152vd-x = ["dep:cortex-m", "stm32-metapac/stm32l152vd-x"]
+stm32l162rc-a = ["dep:cortex-m", "stm32-metapac/stm32l162rc-a"]
+stm32l162vc-a = ["dep:cortex-m", "stm32-metapac/stm32l162vc-a"]
+stm32l162vd-x = ["dep:cortex-m", "stm32-metapac/stm32l162vd-x"]
+stm32h745bg-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h745bg-cm7"]
+stm32h745bg-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h745bg-cm4"]
+stm32h745bi-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h745bi-cm7"]
+stm32h745bi-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h745bi-cm4"]
+stm32h745ig-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h745ig-cm7"]
+stm32h745ig-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h745ig-cm4"]
+stm32h745ii-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h745ii-cm7"]
+stm32h745ii-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h745ii-cm4"]
+stm32h745xg-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h745xg-cm7"]
+stm32h745xg-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h745xg-cm4"]
+stm32h745xi-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h745xi-cm7"]
+stm32h745xi-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h745xi-cm4"]
+stm32h745zg-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h745zg-cm7"]
+stm32h745zg-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h745zg-cm4"]
+stm32h745zi-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h745zi-cm7"]
+stm32h745zi-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h745zi-cm4"]
+stm32h747ag-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h747ag-cm7"]
+stm32h747ag-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h747ag-cm4"]
+stm32h747ai-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h747ai-cm7"]
+stm32h747ai-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h747ai-cm4"]
+stm32h747bg-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h747bg-cm7"]
+stm32h747bg-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h747bg-cm4"]
+stm32h747bi-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h747bi-cm7"]
+stm32h747bi-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h747bi-cm4"]
+stm32h747ig-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h747ig-cm7"]
+stm32h747ig-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h747ig-cm4"]
+stm32h747ii-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h747ii-cm7"]
+stm32h747ii-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h747ii-cm4"]
+stm32h747xg-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h747xg-cm7"]
+stm32h747xg-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h747xg-cm4"]
+stm32h747xi-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h747xi-cm7"]
+stm32h747xi-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h747xi-cm4"]
+stm32h747zi-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h747zi-cm7"]
+stm32h747zi-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h747zi-cm4"]
+stm32h755bi-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h755bi-cm7"]
+stm32h755bi-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h755bi-cm4"]
+stm32h755ii-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h755ii-cm7"]
+stm32h755ii-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h755ii-cm4"]
+stm32h755xi-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h755xi-cm7"]
+stm32h755xi-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h755xi-cm4"]
+stm32h755zi-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h755zi-cm7"]
+stm32h755zi-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h755zi-cm4"]
+stm32h757ai-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h757ai-cm7"]
+stm32h757ai-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h757ai-cm4"]
+stm32h757bi-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h757bi-cm7"]
+stm32h757bi-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h757bi-cm4"]
+stm32h757ii-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h757ii-cm7"]
+stm32h757ii-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h757ii-cm4"]
+stm32h757xi-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h757xi-cm7"]
+stm32h757xi-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h757xi-cm4"]
+stm32h757zi-cm7 = ["dep:cortex-m", "stm32-metapac/stm32h757zi-cm7"]
+stm32h757zi-cm4 = ["dep:cortex-m", "stm32-metapac/stm32h757zi-cm4"]
+stm32c011d6 = ["dep:cortex-m", "stm32-metapac/stm32c011d6"]
+stm32c011f4 = ["dep:cortex-m", "stm32-metapac/stm32c011f4"]
+stm32c011f6 = ["dep:cortex-m", "stm32-metapac/stm32c011f6"]
+stm32c011j4 = ["dep:cortex-m", "stm32-metapac/stm32c011j4"]
+stm32c011j6 = ["dep:cortex-m", "stm32-metapac/stm32c011j6"]
+stm32c031c4 = ["dep:cortex-m", "stm32-metapac/stm32c031c4"]
+stm32c031c6 = ["dep:cortex-m", "stm32-metapac/stm32c031c6"]
+stm32c031f4 = ["dep:cortex-m", "stm32-metapac/stm32c031f4"]
+stm32c031f6 = ["dep:cortex-m", "stm32-metapac/stm32c031f6"]
+stm32c031g4 = ["dep:cortex-m", "stm32-metapac/stm32c031g4"]
+stm32c031g6 = ["dep:cortex-m", "stm32-metapac/stm32c031g6"]
+stm32c031k4 = ["dep:cortex-m", "stm32-metapac/stm32c031k4"]
+stm32c031k6 = ["dep:cortex-m", "stm32-metapac/stm32c031k6"]
+stm32f030c6 = ["dep:cortex-m", "stm32-metapac/stm32f030c6"]
+stm32f030c8 = ["dep:cortex-m", "stm32-metapac/stm32f030c8"]
+stm32f030cc = ["dep:cortex-m", "stm32-metapac/stm32f030cc"]
+stm32f030f4 = ["dep:cortex-m", "stm32-metapac/stm32f030f4"]
+stm32f030k6 = ["dep:cortex-m", "stm32-metapac/stm32f030k6"]
+stm32f030r8 = ["dep:cortex-m", "stm32-metapac/stm32f030r8"]
+stm32f030rc = ["dep:cortex-m", "stm32-metapac/stm32f030rc"]
+stm32f031c4 = ["dep:cortex-m", "stm32-metapac/stm32f031c4"]
+stm32f031c6 = ["dep:cortex-m", "stm32-metapac/stm32f031c6"]
+stm32f031e6 = ["dep:cortex-m", "stm32-metapac/stm32f031e6"]
+stm32f031f4 = ["dep:cortex-m", "stm32-metapac/stm32f031f4"]
+stm32f031f6 = ["dep:cortex-m", "stm32-metapac/stm32f031f6"]
+stm32f031g4 = ["dep:cortex-m", "stm32-metapac/stm32f031g4"]
+stm32f031g6 = ["dep:cortex-m", "stm32-metapac/stm32f031g6"]
+stm32f031k4 = ["dep:cortex-m", "stm32-metapac/stm32f031k4"]
+stm32f031k6 = ["dep:cortex-m", "stm32-metapac/stm32f031k6"]
+stm32f038c6 = ["dep:cortex-m", "stm32-metapac/stm32f038c6"]
+stm32f038e6 = ["dep:cortex-m", "stm32-metapac/stm32f038e6"]
+stm32f038f6 = ["dep:cortex-m", "stm32-metapac/stm32f038f6"]
+stm32f038g6 = ["dep:cortex-m", "stm32-metapac/stm32f038g6"]
+stm32f038k6 = ["dep:cortex-m", "stm32-metapac/stm32f038k6"]
+stm32f042c4 = ["dep:cortex-m", "stm32-metapac/stm32f042c4"]
+stm32f042c6 = ["dep:cortex-m", "stm32-metapac/stm32f042c6"]
+stm32f042f4 = ["dep:cortex-m", "stm32-metapac/stm32f042f4"]
+stm32f042f6 = ["dep:cortex-m", "stm32-metapac/stm32f042f6"]
+stm32f042g4 = ["dep:cortex-m", "stm32-metapac/stm32f042g4"]
+stm32f042g6 = ["dep:cortex-m", "stm32-metapac/stm32f042g6"]
+stm32f042k4 = ["dep:cortex-m", "stm32-metapac/stm32f042k4"]
+stm32f042k6 = ["dep:cortex-m", "stm32-metapac/stm32f042k6"]
+stm32f042t6 = ["dep:cortex-m", "stm32-metapac/stm32f042t6"]
+stm32f048c6 = ["dep:cortex-m", "stm32-metapac/stm32f048c6"]
+stm32f048g6 = ["dep:cortex-m", "stm32-metapac/stm32f048g6"]
+stm32f048t6 = ["dep:cortex-m", "stm32-metapac/stm32f048t6"]
+stm32f051c4 = ["dep:cortex-m", "stm32-metapac/stm32f051c4"]
+stm32f051c6 = ["dep:cortex-m", "stm32-metapac/stm32f051c6"]
+stm32f051c8 = ["dep:cortex-m", "stm32-metapac/stm32f051c8"]
+stm32f051k4 = ["dep:cortex-m", "stm32-metapac/stm32f051k4"]
+stm32f051k6 = ["dep:cortex-m", "stm32-metapac/stm32f051k6"]
+stm32f051k8 = ["dep:cortex-m", "stm32-metapac/stm32f051k8"]
+stm32f051r4 = ["dep:cortex-m", "stm32-metapac/stm32f051r4"]
+stm32f051r6 = ["dep:cortex-m", "stm32-metapac/stm32f051r6"]
+stm32f051r8 = ["dep:cortex-m", "stm32-metapac/stm32f051r8"]
+stm32f051t8 = ["dep:cortex-m", "stm32-metapac/stm32f051t8"]
+stm32f058c8 = ["dep:cortex-m", "stm32-metapac/stm32f058c8"]
+stm32f058r8 = ["dep:cortex-m", "stm32-metapac/stm32f058r8"]
+stm32f058t8 = ["dep:cortex-m", "stm32-metapac/stm32f058t8"]
+stm32f070c6 = ["dep:cortex-m", "stm32-metapac/stm32f070c6"]
+stm32f070cb = ["dep:cortex-m", "stm32-metapac/stm32f070cb"]
+stm32f070f6 = ["dep:cortex-m", "stm32-metapac/stm32f070f6"]
+stm32f070rb = ["dep:cortex-m", "stm32-metapac/stm32f070rb"]
+stm32f071c8 = ["dep:cortex-m", "stm32-metapac/stm32f071c8"]
+stm32f071cb = ["dep:cortex-m", "stm32-metapac/stm32f071cb"]
+stm32f071rb = ["dep:cortex-m", "stm32-metapac/stm32f071rb"]
+stm32f071v8 = ["dep:cortex-m", "stm32-metapac/stm32f071v8"]
+stm32f071vb = ["dep:cortex-m", "stm32-metapac/stm32f071vb"]
+stm32f072c8 = ["dep:cortex-m", "stm32-metapac/stm32f072c8"]
+stm32f072cb = ["dep:cortex-m", "stm32-metapac/stm32f072cb"]
+stm32f072r8 = ["dep:cortex-m", "stm32-metapac/stm32f072r8"]
+stm32f072rb = ["dep:cortex-m", "stm32-metapac/stm32f072rb"]
+stm32f072v8 = ["dep:cortex-m", "stm32-metapac/stm32f072v8"]
+stm32f072vb = ["dep:cortex-m", "stm32-metapac/stm32f072vb"]
+stm32f078cb = ["dep:cortex-m", "stm32-metapac/stm32f078cb"]
+stm32f078rb = ["dep:cortex-m", "stm32-metapac/stm32f078rb"]
+stm32f078vb = ["dep:cortex-m", "stm32-metapac/stm32f078vb"]
+stm32f091cb = ["dep:cortex-m", "stm32-metapac/stm32f091cb"]
+stm32f091cc = ["dep:cortex-m", "stm32-metapac/stm32f091cc"]
+stm32f091rb = ["dep:cortex-m", "stm32-metapac/stm32f091rb"]
+stm32f091rc = ["dep:cortex-m", "stm32-metapac/stm32f091rc"]
+stm32f091vb = ["dep:cortex-m", "stm32-metapac/stm32f091vb"]
+stm32f091vc = ["dep:cortex-m", "stm32-metapac/stm32f091vc"]
+stm32f098cc = ["dep:cortex-m", "stm32-metapac/stm32f098cc"]
+stm32f098rc = ["dep:cortex-m", "stm32-metapac/stm32f098rc"]
+stm32f098vc = ["dep:cortex-m", "stm32-metapac/stm32f098vc"]
+stm32f100c4 = ["dep:cortex-m", "stm32-metapac/stm32f100c4"]
+stm32f100c6 = ["dep:cortex-m", "stm32-metapac/stm32f100c6"]
+stm32f100c8 = ["dep:cortex-m", "stm32-metapac/stm32f100c8"]
+stm32f100cb = ["dep:cortex-m", "stm32-metapac/stm32f100cb"]
+stm32f100r4 = ["dep:cortex-m", "stm32-metapac/stm32f100r4"]
+stm32f100r6 = ["dep:cortex-m", "stm32-metapac/stm32f100r6"]
+stm32f100r8 = ["dep:cortex-m", "stm32-metapac/stm32f100r8"]
+stm32f100rb = ["dep:cortex-m", "stm32-metapac/stm32f100rb"]
+stm32f100rc = ["dep:cortex-m", "stm32-metapac/stm32f100rc"]
+stm32f100rd = ["dep:cortex-m", "stm32-metapac/stm32f100rd"]
+stm32f100re = ["dep:cortex-m", "stm32-metapac/stm32f100re"]
+stm32f100v8 = ["dep:cortex-m", "stm32-metapac/stm32f100v8"]
+stm32f100vb = ["dep:cortex-m", "stm32-metapac/stm32f100vb"]
+stm32f100vc = ["dep:cortex-m", "stm32-metapac/stm32f100vc"]
+stm32f100vd = ["dep:cortex-m", "stm32-metapac/stm32f100vd"]
+stm32f100ve = ["dep:cortex-m", "stm32-metapac/stm32f100ve"]
+stm32f100zc = ["dep:cortex-m", "stm32-metapac/stm32f100zc"]
+stm32f100zd = ["dep:cortex-m", "stm32-metapac/stm32f100zd"]
+stm32f100ze = ["dep:cortex-m", "stm32-metapac/stm32f100ze"]
+stm32f101c4 = ["dep:cortex-m", "stm32-metapac/stm32f101c4"]
+stm32f101c6 = ["dep:cortex-m", "stm32-metapac/stm32f101c6"]
+stm32f101c8 = ["dep:cortex-m", "stm32-metapac/stm32f101c8"]
+stm32f101cb = ["dep:cortex-m", "stm32-metapac/stm32f101cb"]
+stm32f101r4 = ["dep:cortex-m", "stm32-metapac/stm32f101r4"]
+stm32f101r6 = ["dep:cortex-m", "stm32-metapac/stm32f101r6"]
+stm32f101r8 = ["dep:cortex-m", "stm32-metapac/stm32f101r8"]
+stm32f101rb = ["dep:cortex-m", "stm32-metapac/stm32f101rb"]
+stm32f101rc = ["dep:cortex-m", "stm32-metapac/stm32f101rc"]
+stm32f101rd = ["dep:cortex-m", "stm32-metapac/stm32f101rd"]
+stm32f101re = ["dep:cortex-m", "stm32-metapac/stm32f101re"]
+stm32f101rf = ["dep:cortex-m", "stm32-metapac/stm32f101rf"]
+stm32f101rg = ["dep:cortex-m", "stm32-metapac/stm32f101rg"]
+stm32f101t4 = ["dep:cortex-m", "stm32-metapac/stm32f101t4"]
+stm32f101t6 = ["dep:cortex-m", "stm32-metapac/stm32f101t6"]
+stm32f101t8 = ["dep:cortex-m", "stm32-metapac/stm32f101t8"]
+stm32f101tb = ["dep:cortex-m", "stm32-metapac/stm32f101tb"]
+stm32f101v8 = ["dep:cortex-m", "stm32-metapac/stm32f101v8"]
+stm32f101vb = ["dep:cortex-m", "stm32-metapac/stm32f101vb"]
+stm32f101vc = ["dep:cortex-m", "stm32-metapac/stm32f101vc"]
+stm32f101vd = ["dep:cortex-m", "stm32-metapac/stm32f101vd"]
+stm32f101ve = ["dep:cortex-m", "stm32-metapac/stm32f101ve"]
+stm32f101vf = ["dep:cortex-m", "stm32-metapac/stm32f101vf"]
+stm32f101vg = ["dep:cortex-m", "stm32-metapac/stm32f101vg"]
+stm32f101zc = ["dep:cortex-m", "stm32-metapac/stm32f101zc"]
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+stm32f410t8 = ["dep:cortex-m", "stm32-metapac/stm32f410t8"]
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+stm32f411cc = ["dep:cortex-m", "stm32-metapac/stm32f411cc"]
+stm32f411ce = ["dep:cortex-m", "stm32-metapac/stm32f411ce"]
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+stm32f413mh = ["dep:cortex-m", "stm32-metapac/stm32f413mh"]
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+stm32f423mh = ["dep:cortex-m", "stm32-metapac/stm32f423mh"]
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 stm32g081kb = ["dep:cortex-m", "stm32-metapac/stm32g081kb"]
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+stm32l475ve = ["dep:cortex-m", "stm32-metapac/stm32l475ve"]
+stm32l475vg = ["dep:cortex-m", "stm32-metapac/stm32l475vg"]
+stm32l476je = ["dep:cortex-m", "stm32-metapac/stm32l476je"]
+stm32l476jg = ["dep:cortex-m", "stm32-metapac/stm32l476jg"]
+stm32l476me = ["dep:cortex-m", "stm32-metapac/stm32l476me"]
+stm32l476mg = ["dep:cortex-m", "stm32-metapac/stm32l476mg"]
+stm32l476qe = ["dep:cortex-m", "stm32-metapac/stm32l476qe"]
+stm32l476qg = ["dep:cortex-m", "stm32-metapac/stm32l476qg"]
+stm32l476rc = ["dep:cortex-m", "stm32-metapac/stm32l476rc"]
+stm32l476re = ["dep:cortex-m", "stm32-metapac/stm32l476re"]
+stm32l476rg = ["dep:cortex-m", "stm32-metapac/stm32l476rg"]
+stm32l476vc = ["dep:cortex-m", "stm32-metapac/stm32l476vc"]
+stm32l476ve = ["dep:cortex-m", "stm32-metapac/stm32l476ve"]
+stm32l476vg = ["dep:cortex-m", "stm32-metapac/stm32l476vg"]
+stm32l476ze = ["dep:cortex-m", "stm32-metapac/stm32l476ze"]
+stm32l476zg = ["dep:cortex-m", "stm32-metapac/stm32l476zg"]
+stm32l486jg = ["dep:cortex-m", "stm32-metapac/stm32l486jg"]
+stm32l486qg = ["dep:cortex-m", "stm32-metapac/stm32l486qg"]
+stm32l486rg = ["dep:cortex-m", "stm32-metapac/stm32l486rg"]
+stm32l486vg = ["dep:cortex-m", "stm32-metapac/stm32l486vg"]
+stm32l486zg = ["dep:cortex-m", "stm32-metapac/stm32l486zg"]
+stm32l496ae = ["dep:cortex-m", "stm32-metapac/stm32l496ae"]
+stm32l496ag = ["dep:cortex-m", "stm32-metapac/stm32l496ag"]
+stm32l496qe = ["dep:cortex-m", "stm32-metapac/stm32l496qe"]
+stm32l496qg = ["dep:cortex-m", "stm32-metapac/stm32l496qg"]
+stm32l496re = ["dep:cortex-m", "stm32-metapac/stm32l496re"]
+stm32l496rg = ["dep:cortex-m", "stm32-metapac/stm32l496rg"]
+stm32l496ve = ["dep:cortex-m", "stm32-metapac/stm32l496ve"]
+stm32l496vg = ["dep:cortex-m", "stm32-metapac/stm32l496vg"]
+stm32l496wg = ["dep:cortex-m", "stm32-metapac/stm32l496wg"]
+stm32l496ze = ["dep:cortex-m", "stm32-metapac/stm32l496ze"]
+stm32l496zg = ["dep:cortex-m", "stm32-metapac/stm32l496zg"]
+stm32l4a6ag = ["dep:cortex-m", "stm32-metapac/stm32l4a6ag"]
+stm32l4a6qg = ["dep:cortex-m", "stm32-metapac/stm32l4a6qg"]
+stm32l4a6rg = ["dep:cortex-m", "stm32-metapac/stm32l4a6rg"]
+stm32l4a6vg = ["dep:cortex-m", "stm32-metapac/stm32l4a6vg"]
+stm32l4a6zg = ["dep:cortex-m", "stm32-metapac/stm32l4a6zg"]
+stm32l4p5ae = ["dep:cortex-m", "stm32-metapac/stm32l4p5ae"]
+stm32l4p5ag = ["dep:cortex-m", "stm32-metapac/stm32l4p5ag"]
+stm32l4p5ce = ["dep:cortex-m", "stm32-metapac/stm32l4p5ce"]
+stm32l4p5cg = ["dep:cortex-m", "stm32-metapac/stm32l4p5cg"]
+stm32l4p5qe = ["dep:cortex-m", "stm32-metapac/stm32l4p5qe"]
+stm32l4p5qg = ["dep:cortex-m", "stm32-metapac/stm32l4p5qg"]
+stm32l4p5re = ["dep:cortex-m", "stm32-metapac/stm32l4p5re"]
+stm32l4p5rg = ["dep:cortex-m", "stm32-metapac/stm32l4p5rg"]
+stm32l4p5ve = ["dep:cortex-m", "stm32-metapac/stm32l4p5ve"]
+stm32l4p5vg = ["dep:cortex-m", "stm32-metapac/stm32l4p5vg"]
+stm32l4p5ze = ["dep:cortex-m", "stm32-metapac/stm32l4p5ze"]
+stm32l4p5zg = ["dep:cortex-m", "stm32-metapac/stm32l4p5zg"]
+stm32l4q5ag = ["dep:cortex-m", "stm32-metapac/stm32l4q5ag"]
+stm32l4q5cg = ["dep:cortex-m", "stm32-metapac/stm32l4q5cg"]
+stm32l4q5qg = ["dep:cortex-m", "stm32-metapac/stm32l4q5qg"]
+stm32l4q5rg = ["dep:cortex-m", "stm32-metapac/stm32l4q5rg"]
+stm32l4q5vg = ["dep:cortex-m", "stm32-metapac/stm32l4q5vg"]
+stm32l4q5zg = ["dep:cortex-m", "stm32-metapac/stm32l4q5zg"]
+stm32l4r5ag = ["dep:cortex-m", "stm32-metapac/stm32l4r5ag"]
+stm32l4r5ai = ["dep:cortex-m", "stm32-metapac/stm32l4r5ai"]
+stm32l4r5qg = ["dep:cortex-m", "stm32-metapac/stm32l4r5qg"]
+stm32l4r5qi = ["dep:cortex-m", "stm32-metapac/stm32l4r5qi"]
+stm32l4r5vg = ["dep:cortex-m", "stm32-metapac/stm32l4r5vg"]
+stm32l4r5vi = ["dep:cortex-m", "stm32-metapac/stm32l4r5vi"]
+stm32l4r5zg = ["dep:cortex-m", "stm32-metapac/stm32l4r5zg"]
+stm32l4r5zi = ["dep:cortex-m", "stm32-metapac/stm32l4r5zi"]
+stm32l4r7ai = ["dep:cortex-m", "stm32-metapac/stm32l4r7ai"]
+stm32l4r7vi = ["dep:cortex-m", "stm32-metapac/stm32l4r7vi"]
+stm32l4r7zi = ["dep:cortex-m", "stm32-metapac/stm32l4r7zi"]
+stm32l4r9ag = ["dep:cortex-m", "stm32-metapac/stm32l4r9ag"]
+stm32l4r9ai = ["dep:cortex-m", "stm32-metapac/stm32l4r9ai"]
+stm32l4r9vg = ["dep:cortex-m", "stm32-metapac/stm32l4r9vg"]
+stm32l4r9vi = ["dep:cortex-m", "stm32-metapac/stm32l4r9vi"]
+stm32l4r9zg = ["dep:cortex-m", "stm32-metapac/stm32l4r9zg"]
+stm32l4r9zi = ["dep:cortex-m", "stm32-metapac/stm32l4r9zi"]
+stm32l4s5ai = ["dep:cortex-m", "stm32-metapac/stm32l4s5ai"]
+stm32l4s5qi = ["dep:cortex-m", "stm32-metapac/stm32l4s5qi"]
+stm32l4s5vi = ["dep:cortex-m", "stm32-metapac/stm32l4s5vi"]
+stm32l4s5zi = ["dep:cortex-m", "stm32-metapac/stm32l4s5zi"]
+stm32l4s7ai = ["dep:cortex-m", "stm32-metapac/stm32l4s7ai"]
+stm32l4s7vi = ["dep:cortex-m", "stm32-metapac/stm32l4s7vi"]
+stm32l4s7zi = ["dep:cortex-m", "stm32-metapac/stm32l4s7zi"]
+stm32l4s9ai = ["dep:cortex-m", "stm32-metapac/stm32l4s9ai"]
+stm32l4s9vi = ["dep:cortex-m", "stm32-metapac/stm32l4s9vi"]
+stm32l4s9zi = ["dep:cortex-m", "stm32-metapac/stm32l4s9zi"]
+stm32l552cc = ["dep:cortex-m", "stm32-metapac/stm32l552cc"]
+stm32l552ce = ["dep:cortex-m", "stm32-metapac/stm32l552ce"]
+stm32l552me = ["dep:cortex-m", "stm32-metapac/stm32l552me"]
+stm32l552qc = ["dep:cortex-m", "stm32-metapac/stm32l552qc"]
+stm32l552qe = ["dep:cortex-m", "stm32-metapac/stm32l552qe"]
+stm32l552rc = ["dep:cortex-m", "stm32-metapac/stm32l552rc"]
+stm32l552re = ["dep:cortex-m", "stm32-metapac/stm32l552re"]
+stm32l552vc = ["dep:cortex-m", "stm32-metapac/stm32l552vc"]
+stm32l552ve = ["dep:cortex-m", "stm32-metapac/stm32l552ve"]
+stm32l552zc = ["dep:cortex-m", "stm32-metapac/stm32l552zc"]
+stm32l552ze = ["dep:cortex-m", "stm32-metapac/stm32l552ze"]
+stm32l562ce = ["dep:cortex-m", "stm32-metapac/stm32l562ce"]
+stm32l562me = ["dep:cortex-m", "stm32-metapac/stm32l562me"]
+stm32l562qe = ["dep:cortex-m", "stm32-metapac/stm32l562qe"]
+stm32l562re = ["dep:cortex-m", "stm32-metapac/stm32l562re"]
+stm32l562ve = ["dep:cortex-m", "stm32-metapac/stm32l562ve"]
+stm32l562ze = ["dep:cortex-m", "stm32-metapac/stm32l562ze"]
+stm32u535cb = ["dep:cortex-m", "stm32-metapac/stm32u535cb"]
+stm32u535cc = ["dep:cortex-m", "stm32-metapac/stm32u535cc"]
+stm32u535ce = ["dep:cortex-m", "stm32-metapac/stm32u535ce"]
+stm32u535je = ["dep:cortex-m", "stm32-metapac/stm32u535je"]
+stm32u535nc = ["dep:cortex-m", "stm32-metapac/stm32u535nc"]
+stm32u535ne = ["dep:cortex-m", "stm32-metapac/stm32u535ne"]
+stm32u535rb = ["dep:cortex-m", "stm32-metapac/stm32u535rb"]
+stm32u535rc = ["dep:cortex-m", "stm32-metapac/stm32u535rc"]
+stm32u535re = ["dep:cortex-m", "stm32-metapac/stm32u535re"]
+stm32u535vc = ["dep:cortex-m", "stm32-metapac/stm32u535vc"]
+stm32u535ve = ["dep:cortex-m", "stm32-metapac/stm32u535ve"]
+stm32u545ce = ["dep:cortex-m", "stm32-metapac/stm32u545ce"]
+stm32u545je = ["dep:cortex-m", "stm32-metapac/stm32u545je"]
+stm32u545ne = ["dep:cortex-m", "stm32-metapac/stm32u545ne"]
+stm32u545re = ["dep:cortex-m", "stm32-metapac/stm32u545re"]
+stm32u545ve = ["dep:cortex-m", "stm32-metapac/stm32u545ve"]
+stm32u575ag = ["dep:cortex-m", "stm32-metapac/stm32u575ag"]
+stm32u575ai = ["dep:cortex-m", "stm32-metapac/stm32u575ai"]
+stm32u575cg = ["dep:cortex-m", "stm32-metapac/stm32u575cg"]
+stm32u575ci = ["dep:cortex-m", "stm32-metapac/stm32u575ci"]
+stm32u575og = ["dep:cortex-m", "stm32-metapac/stm32u575og"]
+stm32u575oi = ["dep:cortex-m", "stm32-metapac/stm32u575oi"]
+stm32u575qg = ["dep:cortex-m", "stm32-metapac/stm32u575qg"]
+stm32u575qi = ["dep:cortex-m", "stm32-metapac/stm32u575qi"]
+stm32u575rg = ["dep:cortex-m", "stm32-metapac/stm32u575rg"]
+stm32u575ri = ["dep:cortex-m", "stm32-metapac/stm32u575ri"]
+stm32u575vg = ["dep:cortex-m", "stm32-metapac/stm32u575vg"]
+stm32u575vi = ["dep:cortex-m", "stm32-metapac/stm32u575vi"]
+stm32u575zg = ["dep:cortex-m", "stm32-metapac/stm32u575zg"]
+stm32u575zi = ["dep:cortex-m", "stm32-metapac/stm32u575zi"]
+stm32u585ai = ["dep:cortex-m", "stm32-metapac/stm32u585ai"]
+stm32u585ci = ["dep:cortex-m", "stm32-metapac/stm32u585ci"]
+stm32u585oi = ["dep:cortex-m", "stm32-metapac/stm32u585oi"]
+stm32u585qi = ["dep:cortex-m", "stm32-metapac/stm32u585qi"]
+stm32u585ri = ["dep:cortex-m", "stm32-metapac/stm32u585ri"]
+stm32u585vi = ["dep:cortex-m", "stm32-metapac/stm32u585vi"]
+stm32u585zi = ["dep:cortex-m", "stm32-metapac/stm32u585zi"]
+stm32u595ai = ["dep:cortex-m", "stm32-metapac/stm32u595ai"]
+stm32u595aj = ["dep:cortex-m", "stm32-metapac/stm32u595aj"]
+stm32u595qi = ["dep:cortex-m", "stm32-metapac/stm32u595qi"]
+stm32u595qj = ["dep:cortex-m", "stm32-metapac/stm32u595qj"]
+stm32u595ri = ["dep:cortex-m", "stm32-metapac/stm32u595ri"]
+stm32u595rj = ["dep:cortex-m", "stm32-metapac/stm32u595rj"]
+stm32u595vi = ["dep:cortex-m", "stm32-metapac/stm32u595vi"]
+stm32u595vj = ["dep:cortex-m", "stm32-metapac/stm32u595vj"]
+stm32u595zi = ["dep:cortex-m", "stm32-metapac/stm32u595zi"]
+stm32u595zj = ["dep:cortex-m", "stm32-metapac/stm32u595zj"]
+stm32u599bj = ["dep:cortex-m", "stm32-metapac/stm32u599bj"]
+stm32u599ni = ["dep:cortex-m", "stm32-metapac/stm32u599ni"]
+stm32u599nj = ["dep:cortex-m", "stm32-metapac/stm32u599nj"]
+stm32u599vi = ["dep:cortex-m", "stm32-metapac/stm32u599vi"]
+stm32u599vj = ["dep:cortex-m", "stm32-metapac/stm32u599vj"]
+stm32u599zi = ["dep:cortex-m", "stm32-metapac/stm32u599zi"]
+stm32u599zj = ["dep:cortex-m", "stm32-metapac/stm32u599zj"]
+stm32u5a5aj = ["dep:cortex-m", "stm32-metapac/stm32u5a5aj"]
+stm32u5a5qj = ["dep:cortex-m", "stm32-metapac/stm32u5a5qj"]
+stm32u5a5rj = ["dep:cortex-m", "stm32-metapac/stm32u5a5rj"]
+stm32u5a5vj = ["dep:cortex-m", "stm32-metapac/stm32u5a5vj"]
+stm32u5a5zj = ["dep:cortex-m", "stm32-metapac/stm32u5a5zj"]
+stm32u5a9bj = ["dep:cortex-m", "stm32-metapac/stm32u5a9bj"]
+stm32u5a9nj = ["dep:cortex-m", "stm32-metapac/stm32u5a9nj"]
+stm32u5a9vj = ["dep:cortex-m", "stm32-metapac/stm32u5a9vj"]
+stm32u5a9zj = ["dep:cortex-m", "stm32-metapac/stm32u5a9zj"]
+stm32wb10cc = ["dep:cortex-m", "stm32-metapac/stm32wb10cc"]
+stm32wb15cc = ["dep:cortex-m", "stm32-metapac/stm32wb15cc"]
+stm32wb30ce = ["dep:cortex-m", "stm32-metapac/stm32wb30ce"]
+stm32wb35cc = ["dep:cortex-m", "stm32-metapac/stm32wb35cc"]
+stm32wb35ce = ["dep:cortex-m", "stm32-metapac/stm32wb35ce"]
+stm32wb50cg = ["dep:cortex-m", "stm32-metapac/stm32wb50cg"]
+stm32wb55cc = ["dep:cortex-m", "stm32-metapac/stm32wb55cc"]
+stm32wb55ce = ["dep:cortex-m", "stm32-metapac/stm32wb55ce"]
+stm32wb55cg = ["dep:cortex-m", "stm32-metapac/stm32wb55cg"]
+stm32wb55rc = ["dep:cortex-m", "stm32-metapac/stm32wb55rc"]
+stm32wb55re = ["dep:cortex-m", "stm32-metapac/stm32wb55re"]
+stm32wb55rg = ["dep:cortex-m", "stm32-metapac/stm32wb55rg"]
+stm32wb55vc = ["dep:cortex-m", "stm32-metapac/stm32wb55vc"]
+stm32wb55ve = ["dep:cortex-m", "stm32-metapac/stm32wb55ve"]
+stm32wb55vg = ["dep:cortex-m", "stm32-metapac/stm32wb55vg"]
+stm32wb55vy = ["dep:cortex-m", "stm32-metapac/stm32wb55vy"]
+stm32wl54cc-cm4 = ["dep:cortex-m", "stm32-metapac/stm32wl54cc-cm4"]
+stm32wl54cc-cm0p = ["dep:cortex-m", "stm32-metapac/stm32wl54cc-cm0p"]
+stm32wl54jc-cm4 = ["dep:cortex-m", "stm32-metapac/stm32wl54jc-cm4"]
+stm32wl54jc-cm0p = ["dep:cortex-m", "stm32-metapac/stm32wl54jc-cm0p"]
+stm32wl55cc-cm4 = ["dep:cortex-m", "stm32-metapac/stm32wl55cc-cm4"]
+stm32wl55cc-cm0p = ["dep:cortex-m", "stm32-metapac/stm32wl55cc-cm0p"]
+stm32wl55jc-cm4 = ["dep:cortex-m", "stm32-metapac/stm32wl55jc-cm4"]
+stm32wl55jc-cm0p = ["dep:cortex-m", "stm32-metapac/stm32wl55jc-cm0p"]
+stm32wle4c8 = ["dep:cortex-m", "stm32-metapac/stm32wle4c8"]
+stm32wle4cb = ["dep:cortex-m", "stm32-metapac/stm32wle4cb"]
+stm32wle4cc = ["dep:cortex-m", "stm32-metapac/stm32wle4cc"]
+stm32wle4j8 = ["dep:cortex-m", "stm32-metapac/stm32wle4j8"]
+stm32wle4jb = ["dep:cortex-m", "stm32-metapac/stm32wle4jb"]
+stm32wle4jc = ["dep:cortex-m", "stm32-metapac/stm32wle4jc"]
+stm32wle5c8 = ["dep:cortex-m", "stm32-metapac/stm32wle5c8"]
+stm32wle5cb = ["dep:cortex-m", "stm32-metapac/stm32wle5cb"]
+stm32wle5cc = ["dep:cortex-m", "stm32-metapac/stm32wle5cc"]
+stm32wle5j8 = ["dep:cortex-m", "stm32-metapac/stm32wle5j8"]
+stm32wle5jb = ["dep:cortex-m", "stm32-metapac/stm32wle5jb"]
+stm32wle5jc = ["dep:cortex-m", "stm32-metapac/stm32wle5jc"]
diff --git a/rtic-monotonics/build.rs b/rtic-monotonics/build.rs
new file mode 100644
index 0000000000..a2ed570798
--- /dev/null
+++ b/rtic-monotonics/build.rs
@@ -0,0 +1,22 @@
+fn main() {
+    // feature=["stm32g081kb"] etc.
+    let stm32_chip: Vec<_> = std::env::vars()
+        .map(|(a, _)| a)
+        .filter(|x| {
+            !x.starts_with("CARGO_FEATURE_STM32_METAPAC")
+                && !x.starts_with("CARGO_FEATURE_STM32_TIM")
+                && x.starts_with("CARGO_FEATURE_STM32")
+        })
+        .collect();
+
+    match stm32_chip.len() {
+        0 => {
+            // Not using stm32.
+        }
+        1 => {
+            // Allows to just use #[cfg(stm32)] if one of the stm32 chips is used.
+            println!("cargo:rustc-cfg=stm32");
+        }
+        _ => panic!("multiple stm32xx definitions {:?}", stm32_chip),
+    }
+}
diff --git a/rtic-monotonics/src/lib.rs b/rtic-monotonics/src/lib.rs
index b5cc5421b7..b34f9d6259 100644
--- a/rtic-monotonics/src/lib.rs
+++ b/rtic-monotonics/src/lib.rs
@@ -46,7 +46,8 @@ pub mod rp2040;
 ))]
 pub mod nrf;
 
-#[cfg(any(feature = "stm32g081kb",))]
+// Notice that `stm32` is not a feature, it is a compilation flag set in build.rs.
+#[cfg(stm32)]
 pub mod stm32;
 
 #[allow(dead_code)]
@@ -64,7 +65,7 @@ pub(crate) const fn cortex_logical2hw(logical: u8, nvic_prio_bits: u8) -> u8 {
     feature = "nrf5340-app",
     feature = "nrf5340-net",
     feature = "nrf9160",
-    feature = "stm32g081kb",
+    stm32,
 ))]
 pub(crate) unsafe fn set_monotonic_prio(
     prio_bits: u8,
diff --git a/rtic-monotonics/src/stm32.rs b/rtic-monotonics/src/stm32.rs
index e496e56b84..780ecbe443 100644
--- a/rtic-monotonics/src/stm32.rs
+++ b/rtic-monotonics/src/stm32.rs
@@ -61,6 +61,7 @@ macro_rules! __internal_create_stm32_timer_interrupt {
 }
 
 /// Register TIM2 interrupt for the monotonic.
+#[cfg(feature = "stm32_tim2")]
 #[macro_export]
 macro_rules! create_stm32_tim2_monotonic_token {
     () => {{
@@ -69,6 +70,7 @@ macro_rules! create_stm32_tim2_monotonic_token {
 }
 
 /// Register TIM3 interrupt for the monotonic.
+#[cfg(feature = "stm32_tim3")]
 #[macro_export]
 macro_rules! create_stm32_tim3_monotonic_token {
     () => {{
@@ -76,8 +78,55 @@ macro_rules! create_stm32_tim3_monotonic_token {
     }};
 }
 
+/// Register TIM4 interrupt for the monotonic.
+#[cfg(feature = "stm32_tim4")]
+#[macro_export]
+macro_rules! create_stm32_tim4_monotonic_token {
+    () => {{
+        $crate::__internal_create_stm32_timer_interrupt!(Tim4, TIM4, Tim4Token)
+    }};
+}
+
+/// Register TIM5 interrupt for the monotonic.
+#[cfg(feature = "stm32_tim5")]
+#[macro_export]
+macro_rules! create_stm32_tim5_monotonic_token {
+    () => {{
+        $crate::__internal_create_stm32_timer_interrupt!(Tim5, TIM5, Tim5Token)
+    }};
+}
+
+/// Register TIM12 interrupt for the monotonic.
+#[cfg(feature = "stm32_tim12")]
+#[macro_export]
+macro_rules! create_stm32_tim12_monotonic_token {
+    () => {{
+        $crate::__internal_create_stm32_timer_interrupt!(Tim12, TIM12, Tim12Token)
+    }};
+}
+
+/// Register TIM15 interrupt for the monotonic.
+#[cfg(feature = "stm32_tim15")]
+#[macro_export]
+macro_rules! create_stm32_tim15_monotonic_token {
+    () => {{
+        $crate::__internal_create_stm32_timer_interrupt!(Tim15, TIM15, Tim15Token)
+    }};
+}
+
+// Creates `enable_timer()` function which enables timer in RCC.
+macro_rules! enable_timer {
+    ($apbenrX:ident, $set_timXen:ident, $apbrstrX:ident, $set_timXrst:ident) => {
+        fn enable_timer() {
+            pac::RCC.$apbenrX().modify(|r| r.$set_timXen(true));
+            pac::RCC.$apbrstrX().modify(|r| r.$set_timXrst(true));
+            pac::RCC.$apbrstrX().modify(|r| r.$set_timXrst(false));
+        }
+    };
+}
+
 macro_rules! make_timer {
-    ($mono_name:ident, $timer:ident, $bits:ident, $set_tim_en:ident, $set_tim_rst:ident, $overflow:ident, $tq:ident$(, doc: ($($doc:tt)*))?) => {
+    ($mono_name:ident, $timer:ident, $bits:ident, $overflow:ident, $tq:ident$(, doc: ($($doc:tt)*))?) => {
         /// Monotonic timer queue implementation.
         $(
             #[cfg_attr(docsrs, doc(cfg($($doc)*)))]
@@ -91,12 +140,12 @@ macro_rules! make_timer {
         static $tq: TimerQueue<$mono_name> = TimerQueue::new();
 
         impl $mono_name {
-            /// Start monotonic timer. Must be called only once.
-            /// `tim_clock_hz` shows to which frequency `TIMx` clock source is configured.
+            /// Starts the monotonic timer.
+            /// - `tim_clock_hz`: `TIMx` peripheral clock frequency.
+            /// - `_interrupt_token`: Required for correct timer interrupt handling.
+            /// This method must be called only once.
             pub fn start(tim_clock_hz: u32, _interrupt_token: impl crate::InterruptToken<Self>) {
-                pac::RCC.apbenr1().modify(|r| r.$set_tim_en(true));
-                pac::RCC.apbrstr1().modify(|r| r.$set_tim_rst(true));
-                pac::RCC.apbrstr1().modify(|r| r.$set_tim_rst(false));
+                enable_timer();
 
                 $timer.cr1().modify(|r| r.set_cen(false));
 
@@ -229,21 +278,32 @@ macro_rules! make_timer {
     };
 }
 
-make_timer!(
-    Tim2,
-    TIM2,
-    u32,
-    set_tim2en,
-    set_tim2rst,
-    TIMER2_OVERFLOWS,
-    TIMER2_TQ
-);
-make_timer!(
-    Tim3,
-    TIM3,
-    u16,
-    set_tim3en,
-    set_tim3rst,
-    TIMER3_OVERFLOWS,
-    TIMER3_TQ
-);
+#[cfg(feature = "stm32_tim2")]
+enable_timer!(apbenr1, set_tim2en, apbrstr1, set_tim2rst);
+#[cfg(feature = "stm32_tim2")]
+make_timer!(Tim2, TIM2, u32, TIMER2_OVERFLOWS, TIMER2_TQ);
+
+#[cfg(feature = "stm32_tim3")]
+enable_timer!(apbenr1, set_tim3en, apbrstr1, set_tim3rst);
+#[cfg(feature = "stm32_tim3")]
+make_timer!(Tim3, TIM3, u16, TIMER3_OVERFLOWS, TIMER3_TQ);
+
+#[cfg(feature = "stm32_tim4")]
+enable_timer!(apbenr1, set_tim4en, apbrstr1, set_tim4rst);
+#[cfg(feature = "stm32_tim4")]
+make_timer!(Tim4, TIM4, u16, TIMER4_OVERFLOWS, TIMER4_TQ);
+
+#[cfg(feature = "stm32_tim5")]
+enable_timer!(apbenr1, set_tim5en, apbrstr1, set_tim5rst);
+#[cfg(feature = "stm32_tim5")]
+make_timer!(Tim5, TIM5, u16, TIMER5_OVERFLOWS, TIMER5_TQ);
+
+#[cfg(feature = "stm32_tim12")]
+enable_timer!(apb1enr, set_tim12en, apb1rstr, set_tim12rst);
+#[cfg(feature = "stm32_tim12")]
+make_timer!(Tim12, TIM12, u16, TIMER12_OVERFLOWS, TIMER12_TQ);
+
+#[cfg(feature = "stm32_tim15")]
+enable_timer!(apbenr2, set_tim15en, apbrstr2, set_tim15rst);
+#[cfg(feature = "stm32_tim15")]
+make_timer!(Tim15, TIM15, u16, TIMER15_OVERFLOWS, TIMER15_TQ);