Brutally yank out multicore

macros/src/codegen/pre_init.rs

@@ -6,60 +6,44 @@ use crate::{analyze::Analysis, check::Extra, codegen::util};
 
 /// Generates code that runs before `#[init]`
 pub fn codegen(
-    core: u8,
     app: &App,
     analysis: &Analysis,
     extra: &Extra,
-) -> (
-    // `const_app_pre_init` -- `static` variables for barriers
-    Vec<TokenStream2>,
+) ->
     // `pre_init_stmts`
-    Vec<TokenStream2>,
-) {
-    let mut const_app = vec![];
+    Vec<TokenStream2>
+{
     let mut stmts = vec![];
 
     // disable interrupts -- `init` must run with interrupts disabled
     stmts.push(quote!(rtic::export::interrupt::disable();));
 
-    // populate this core `FreeQueue`s
-    for (name, senders) in &analysis.free_queues {
+    // populate the FreeQueue
+    for fq in &analysis.free_queues {
+        // Get the task name
+        let name = fq.0;
         let task = &app.software_tasks[name];
         let cap = task.args.capacity;
 
-        for &sender in senders.keys() {
-            if sender == core {
-                let fq = util::fq_ident(name, sender);
+        let fq_ident = util::fq_ident(name);
 
-                stmts.push(quote!(
-                    (0..#cap).for_each(|i| #fq.enqueue_unchecked(i));
-                ));
-            }
-        }
-    }
-
-    if app.args.cores == 1 {
         stmts.push(quote!(
-            // To set the variable in cortex_m so the peripherals cannot be taken multiple times
-            let mut core: rtic::export::Peripherals = rtic::export::Peripherals::steal().into();
-        ));
-    } else {
-        stmts.push(quote!(
-            // NOTE(transmute) to avoid debug_assertion in multi-core mode
-            // (This code will go away when we drop multi-core mode)
-            let mut core: rtic::export::Peripherals = core::mem::transmute(());
+            (0..#cap).for_each(|i| #fq_ident.enqueue_unchecked(i));
         ));
     }
 
+    stmts.push(quote!(
+        // To set the variable in cortex_m so the peripherals cannot be taken multiple times
+        let mut core: rtic::export::Peripherals = rtic::export::Peripherals::steal().into();
+    ));
+
     let device = extra.device;
     let nvic_prio_bits = quote!(#device::NVIC_PRIO_BITS);
 
     // unmask interrupts and set their priorities
     for (&priority, name) in analysis
         .interrupts
-        .get(&core)
         .iter()
-        .flat_map(|interrupts| *interrupts)
         .chain(app.hardware_tasks.values().flat_map(|task| {
             if !util::is_exception(&task.args.binds) {
                 Some((&task.args.priority, &task.args.binds))
@@ -73,7 +57,7 @@ pub fn codegen(
         stmts.push(quote!(let _ = [(); ((1 << #nvic_prio_bits) - #priority as usize)];));
 
         // NOTE this also checks that the interrupt exists in the `Interrupt` enumeration
-        let interrupt = util::interrupt_ident(core, app.args.cores);
+        let interrupt = util::interrupt_ident();
         stmts.push(quote!(
             core.NVIC.set_priority(
                 #device::#interrupt::#name,
@@ -88,6 +72,7 @@ pub fn codegen(
 
     // cross-spawn barriers: now that priorities have been set and the interrupts have been unmasked
     // we are ready to receive messages from *other* cores
+    /*
     if analysis.spawn_barriers.contains_key(&core) {
         let sb = util::spawn_barrier(core);
         let shared = if cfg!(feature = "heterogeneous") {
@@ -108,6 +93,7 @@ pub fn codegen(
             #sb.release();
         ));
     }
+    */
 
     // set exception priorities
     for (name, priority) in app.hardware_tasks.values().filter_map(|task| {
@@ -126,8 +112,8 @@ pub fn codegen(
         );));
     }
 
-    // initialize the SysTick
-    if let Some(tq) = analysis.timer_queues.get(&core) {
+    // initialize the SysTick if there exist a TimerQueue
+    if let Some(tq) = analysis.timer_queues.first() {
         let priority = tq.priority;
 
         // compile time assert that this priority is supported by the device
@@ -146,11 +132,12 @@ pub fn codegen(
     }
 
     // if there's no user `#[idle]` then optimize returning from interrupt handlers
-    if app.idles.get(&core).is_none() {
+    if app.idles.is_empty() {
         // Set SLEEPONEXIT bit to enter sleep mode when returning from ISR
         stmts.push(quote!(core.SCB.scr.modify(|r| r | 1 << 1);));
     }
 
+    /*
     // cross-spawn barriers: wait until other cores are ready to receive messages
     for (&receiver, senders) in &analysis.spawn_barriers {
         // only block here if `init` can send messages to `receiver`
@@ -162,6 +149,7 @@ pub fn codegen(
             ));
         }
     }
+    */
 
-    (const_app, stmts)
+    stmts
 }