From 70ebcc409ff4e34764337a978882a25f34484c4f Mon Sep 17 00:00:00 2001 From: n8tlarsen <96437952+n8tlarsen@users.noreply.github.com> Date: Mon, 19 Dec 2022 18:16:25 -0600 Subject: [PATCH] Clarify BASEPRI and NVIC interaction MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Henrik Tjäder --- book/en/src/internals/targets.md | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/book/en/src/internals/targets.md b/book/en/src/internals/targets.md index bdfb24bb2d..606191d20f 100644 --- a/book/en/src/internals/targets.md +++ b/book/en/src/internals/targets.md @@ -28,8 +28,10 @@ This implementation is covered in depth by Chapter 4.5 of this book. ## Source Masking -Since there is no hardware support for a priority ceiling, RTIC must instead rely on the Nested -Vectored Interrupt Controller (NVIC) present in the core architecture. Consider Figure 1 below, +Without a `BASEPRI` register which allows for directly setting a priority ceiling in the Nested +Vectored Interrupt Controller (NVIC), RTIC must instead rely on disabling (masking) interrupts. + +Consider Figure 1 below, showing two tasks A and B where A has higher priority but shares a resource with B. #### *Figure 1: Shared Resources and Source Masking*