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RISC-V support over CLINT (#815)
* Rebase to master * using interrupt_mod * bug fixes * fix other backends * Add changelog * forgot about rtic-macros * backend-specific configuration * core peripherals optional over macro argument * pre_init_preprocessing binding * CI for RISC-V (WIP) * separation of concerns * add targets for RISC-V examples * remove qemu feature * prepare examples folder * move examples all together * move ci out of examples * minor changes * add cortex-m * new xtask: proof of concept * fix build.yml * feature typo * clean rtic examples * reproduce weird issue * remove unsafe code in user app * update dependencies * allow builds on riscv32imc * let's fix QEMU * Update .github/workflows/build.yml Co-authored-by: Henrik Tjäder <henrik@tjaders.com> * New build.rs * removing test features * adapt ui test to new version of clippy * add more examples to RISC-V backend * proper configuration of heapless for riscv32imc * opt-out examples for riscv32imc * point to new version of riscv-slic * adapt new macro bindings * adapt examples and CI to stable * fix cortex-m CI * Review --------- Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
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166 changed files with 2322 additions and 315 deletions
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@ -55,10 +55,20 @@ mod esp32c3 {
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Ident::new("Interrupt", span)
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}
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pub fn interrupt_mod(app: &App) -> TokenStream2 {
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let device = &app.args.device;
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let interrupt = interrupt_ident();
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quote!(#device::#interrupt)
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}
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pub fn extra_assertions(_: &App, _: &SyntaxAnalysis) -> Vec<TokenStream2> {
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vec![]
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}
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pub fn pre_init_preprocessing(_app: &mut App, _analysis: &SyntaxAnalysis) -> parse::Result<()> {
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Ok(())
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}
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pub fn pre_init_checks(app: &App, _: &SyntaxAnalysis) -> Vec<TokenStream2> {
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let mut stmts = vec![];
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// check that all dispatchers exists in the `Interrupt` enumeration regardless of whether
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@ -232,3 +242,7 @@ mod esp32c3 {
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stmts
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}
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}
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pub fn extra_modules(_app: &App, _analysis: &SyntaxAnalysis) -> Vec<TokenStream2> {
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vec![]
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}
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