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https://github.com/rtic-rs/rtic.git
synced 2024-11-23 20:22:51 +01:00
rename rtfm::critical to rtfm::atomic, touch up the documentation
This commit is contained in:
Jorge Aparicio
parent
840c32060b
commit
404dde6f2a
1 changed files with 91 additions and 43 deletions
128
src/lib.rs
128
src/lib.rs
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@ -1,12 +1,13 @@
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//! RTFM: Real Time For the Masses (ARM Cortex-M edition)
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//!
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//! RTFM is a framework for building event-driven applications for ARM Cortex-M
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//! microcontrollers.
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//! `cortex-m-rtfm` is a framework for building concurrent applications for ARM
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//! Cortex-M microcontrollers.
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//!
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//! This crate is based on the RTFM framework created by [prof. Per
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//! This crate is based on [the RTFM framework] created by [prof. Per
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//! Lindgren][per] and uses a simplified version of the Stack Resource Policy as
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//! scheduling policy. Check the [references] for details.
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//! scheduling policy (check the [references] for details).
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//!
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//! [the RTFM framework]: http://www.rtfm-lang.org/
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//! [per]: https://www.ltu.se/staff/p/pln-1.11258?l=en
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//! [references]: ./index.html#references
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//!
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@ -14,13 +15,16 @@
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//!
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//! - **Event triggered tasks** as the unit of concurrency.
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//! - Supports prioritization of tasks and, thus, **preemptive multitasking**.
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//! - **Data race free memory sharing** through fine grained *non global*
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//! critical sections.
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//! - **Efficient data race free memory sharing** through fine grained *non
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//! global* critical sections.
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//! - **Deadlock free execution** guaranteed at compile time.
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//! - **Minimal overhead** as the scheduler has no software component / runtime;
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//! the hardware does all the scheduling.
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//! - Full support for all Cortex M3, M4 and M7 devices. M0(+) is also supported
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//! but the whole API is not available (due to missing hardware features).
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//! - **Minimal scheduling overhead** as the scheduler has no "software
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//! component"; the hardware does all the scheduling.
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//! - **Highly efficient memory usage**. All the tasks share the call stack and
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//! there's no hard dependency on a dynamic allocator.
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//! - **All Cortex M3, M4 and M7 devices are fully supported**. M0(+) is
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//! partially supported as the whole API is not available (due to missing
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//! hardware features).
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//! - The number of task priority levels is configurable at compile time through
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//! the `P2` (4 levels), `P3` (8 levels), etc. Cargo features. The number of
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//! priority levels supported by the hardware is device specific but this
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@ -55,6 +59,7 @@
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//! ## Zero tasks
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//!
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//! ``` ignore
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//! #![feature(used)]
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//! #![no_std]
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//!
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//! #[macro_use] // for the `hprintln!` macro
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@ -101,7 +106,7 @@
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//! structure into your program:
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//!
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//! - `init`, the initialization phase, runs first. This function is executed
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//! inside a *global* critical section and can't be preempted.
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//! "atomically", in the sense that no task / interrupt can preempt it.
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//!
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//! - `idle`, a never ending function that runs after `init`.
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//!
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@ -110,6 +115,8 @@
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//! # One task
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//!
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//! ``` ignore
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//! #![feature(const_fn)]
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//! #![feature(used)]
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//! #![no_std]
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//!
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//! extern crate cortex_m_rt;
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@ -129,7 +136,9 @@
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//! // IDLE LOOP
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//! fn idle(_priority: P0) -> ! {
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//! // Sleep
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//! loop { rtfm::wfi() }
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//! loop {
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//! rtfm::wfi();
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//! }
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//! }
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//!
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//! // TASKS
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@ -173,6 +182,8 @@
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//! # Two "serial" tasks
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//!
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//! ``` ignore
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//! #![feature(const_fn)]
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//! #![feature(used)]
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//! #![no_std]
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//!
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//! extern crate cortex_m_rt;
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@ -203,6 +214,17 @@
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//! // Data shared between tasks `t1` and `t2`
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//! static COUNTER: Resource<Cell<u32>, C1> = Resource::new(Cell::new(0));
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//!
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//! fn init(priority: P0, ceiling: &C16) {
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//! // ..
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//! }
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//!
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//! fn idle(priority: P0) -> ! {
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//! // Sleep
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//! loop {
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//! rtfm::wfi();
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//! }
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//! }
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//!
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//! fn t1(_task: Tim6Dacunder, priority: P1) {
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//! let ceiling = priority.as_ceiling();
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//!
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@ -223,13 +245,13 @@
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//! Here we declare two tasks, `t1` and `t2`; both with a priority of 1 (`P1`).
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//! As both tasks have the same priority, we say that they are *serial* tasks in
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//! the sense that `t1` can only run *after* `t2` is done and vice versa; i.e.
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//! there's no preemption.
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//! no preemption between them is possible.
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//!
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//! To share data between these two tasks, we use the
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//! [`Resource`](./struct.Resource.html) abstraction. As the tasks can't preempt
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//! each other, they can access the `COUNTER` resource using the zero cost
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//! [`access`](./struct.Resource.html#method.access) method -- no
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//! synchronization needed.
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//! synchronization is required.
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//!
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//! `COUNTER` has an extra type parameter: `C1`. This is the *ceiling* of the
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//! resource. For now suffices to say that the ceiling must be the maximum of
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@ -240,6 +262,8 @@
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//! # Preemptive multitasking
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//!
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//! ``` ignore
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//! #![feature(const_fn)]
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//! #![feature(used)]
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//! #![no_std]
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//!
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//! extern crate cortex_m_rt;
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@ -250,9 +274,7 @@
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//! use core::cell::Cell;
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//!
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//! use stm32f30x::interrupt::{Tim6Dacunder, Tim7};
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//! use rtfm::{C2, C16, P0, P1, P2, Resource};
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//!
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//! // omitted: `idle`, `init`
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//! use rtfm::{C1, C16, C2, P0, P1, P2, Resource};
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//!
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//! tasks!(stm32f30x, {
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//! t1: Task {
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@ -269,16 +291,29 @@
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//!
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//! static COUNTER: Resource<Cell<u32>, C2> = Resource::new(Cell::new(0));
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//!
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//! fn init(priority: P0, ceiling: &C16) {
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//! // ..
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//! }
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//!
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//! fn idle(priority: P0) -> ! {
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//! // Sleep
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//! loop {
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//! rtfm::wfi();
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//! }
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//! }
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//!
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//! fn t1(_task: Tim6Dacunder, priority: P1) {
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//! // ..
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//!
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//! let ceiling: &C1 = priority.as_ceiling();
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//!
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//! ceiling.raise(&COUNTER, |ceiling: &C2| {
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//! ceiling.raise(
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//! &COUNTER, |ceiling: &C2| {
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//! let counter = COUNTER.access(&priority, ceiling);
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//!
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//! counter.set(counter.get() + 1);
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//! });
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//! }
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//! );
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//!
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//! // ..
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//! }
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@ -300,39 +335,48 @@
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//! To avoid data races, `t1` must modify `COUNTER` in an atomic way; i.e. `t2`
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//! most not preempt `t1` while `COUNTER` is being modified. This is
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//! accomplished by [`raise`](./struct.C.html#method.raise)-ing the `ceiling`.
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//! This creates a critical section, denoted by a closure, for whose span
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//! This creates a critical section, denoted by a closure; for whose execution,
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//! `COUNTER` is accessible but `t2` is blocked from preempting `t1`.
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//!
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//! How `t2` accesses `COUNTER` remains unchanged. Since `t1` can't preempt `t2`
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//! due to the differences in priority; no critical section is needed in `t2`.
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//!
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//! Note that the ceiling of `COUNTER` had to change to `C2`. This is required
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//! because the ceiling must be the maximum between `P1` and `P2`.
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//! Note that the ceiling of `COUNTER` had to be changed to `C2`. This is
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//! required because the ceiling must be the maximum between `P1` and `P2`.
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//!
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//! Finally, it should be noted that the critical section in `t1` will only
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//! block tasks with a priority of 2 or lower. This is exactly what the ceiling
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//! represents: it's the "bar" that a task priority must pass in order to be
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//! able to preempt the current task / critical section.
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//! able to preempt the current task / critical section. Note that a task with
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//! e.g. a priority of 3 (`P3`) effectively imposes a ceiling of 3 (`C3`)
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//! because only other task with a priority of 4 or greater can preempt it.
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//!
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//! # Peripherals as resources
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//!
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//! ``` ignore
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//! #![feature(const_fn)]
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//! #![feature(used)]
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//! #![no_std]
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//!
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//! extern crate cortex_m_rt;
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//! #[macro_use]
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//! extern crate cortex_m_rtfm as rtfm;
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//! extern crate stm32f100xx;
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//! extern crate stm32f30x;
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//!
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//! use rtfm::{C0, C16, P0, Peripheral};
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//!
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//! static GPIOA: Peripheral<stm32f100xx::Gpioa, C0> =
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//! unsafe { Peripheral::new(stm32f100xx::GPIOA) };
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//! peripherals!(stm32f30x, {
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//! GPIOA: Peripheral {
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//! register_block: Gpioa,
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//! ceiling: C0,
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//! },
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//! RCC: Peripheral {
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//! register_block: Rcc,
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//! ceiling: C0,
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//! },
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//! });
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//!
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//! static RCC: Peripheral<stm32f100xx::Rcc, C0> =
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//! unsafe { Peripheral::new(stm32f100xx::RCC) };
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//!
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//! tasks!(stm32f100xx, {});
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//! tasks!(stm32f30x, {});
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//!
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//! fn init(priority: P0, ceiling: &C16) {
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//! let gpioa = GPIOA.access(&priority, &ceiling);
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//!
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//! fn idle(_priority: P0) -> ! {
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//! // Sleep
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//! loop { rtfm::wfi() }
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//! loop {
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//! rtfm::wfi();
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//! }
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//! }
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//! ```
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//!
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@ -352,8 +398,8 @@
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//! [`Peripheral`](./struct.Peripheral.html) abstraction.
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//!
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//! `Peripheral` and `Resource` has pretty much the same API except that
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//! `Peripheral.new` is `unsafe`. Care must be taken to NOT alias peripherals;
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//! i.e. don't create two `Peripheral`s that point to the same register block.
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//! `Peripheral` instances must be declared using the
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//! [`peripherals!`](./macro.peripherals.html) macro.
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//!
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//! # References
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//!
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@ -537,10 +583,10 @@ impl<Periph, RC> Peripheral<Periph, C<RC>> {
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unsafe impl<T, C> Sync for Peripheral<T, C> {}
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/// Runs the closure `f` in a *global* critical section
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/// Runs the closure `f` "atomically"
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///
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/// No task can preempt this critical section
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pub fn critical<R, F>(f: F) -> R
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/// No task can preempt the execution of the closure
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pub fn atomic<R, F>(f: F) -> R
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where
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F: FnOnce(&CMAX) -> R,
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{
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r
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}
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/// Disables the `task`
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/// Disables a `task`
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///
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/// The task won't run even if the underlying interrupt is raised
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pub fn disable<T, TP>(_task: fn(T, P<TP>))
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@ -572,7 +618,7 @@ where
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unsafe { (*_NVIC.get()).disable(_task) }
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}
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/// Enables the `task`
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/// Enables a `task`
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pub fn enable<T, TP>(_task: fn(T, P<TP>))
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where
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T: Context + Nr,
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@ -791,7 +837,9 @@ macro_rules! peripherals {
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///
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/// fn idle(priority: P0) -> ! {
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/// // Sleep
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/// loop { rtfm::wfi() }
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/// loop {
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/// rtfm::wfi();
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/// }
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/// }
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///
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/// // NOTE signature must match the tasks! declaration
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},)*
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}) => {
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fn main() {
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$crate::critical(|cmax| {
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$crate::atomic(|cmax| {
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fn validate_signature(_: fn($crate::P0, &$crate::CMAX)) {}
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validate_signature(init);
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