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[monotonics] Fix STM32 read-modify-write race condition (#984)

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* Fix stm32 read-modify-write problem

The `SR` register for STM32 clears when writing a zero to a bit.
Therefore, all registers that should not be cleared need to be `1`.

`modify` here caused a read-modify-write error that could clear
unrelated flags.

* Add changelog

* Make initialization more deterministic

* Update changelog

* Beautification in comments

---------

Co-authored-by: Martin Stumpf <martin.stumpf@vected.de>
This commit is contained in:
Finomnis 2024-10-23 21:28:42 +02:00 committed by GitHub
parent 0f532c6b48
commit 3dfef74a4c
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2 changed files with 28 additions and 6 deletions
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5
rtic-monotonics/CHANGELOG.md
View file

@ -15,6 +15,11 @@ For each category, *Added*, *Changed*, *Fixed* add new entries at the top!
- Update `esp32c3` dependency
### Fixed
- STM32: Make initialization more deterministic
- STM32: Fix race condition that caused missed interrupts
## v2.0.2 - 2024-07-05
### Added

29
rtic-monotonics/src/stm32.rs
View file

@ -246,9 +246,17 @@ macro_rules! make_timer {
// Trigger an update event to load the prescaler value to the clock.
$timer.egr().write(|r| r.set_ug(true));
// The above line raises an update event which will indicate that the timer is already finished.
// Since this is not the case, it should be cleared.
$timer.sr().modify(|r| r.set_uif(false));
// Clear timer value so it is known that we are at the first half period
$timer.cnt().write(|r| r.set_cnt(1));
// Triggering the update event might have raised overflow interrupts.
// Clear them to return to a known state.
$timer.sr().write(|r| {
r.0 = !0;
r.set_uif(false);
r.set_ccif(0, false);
r.set_ccif(1, false);
});
$tq.initialize(Self {});
$overflow.store(0, Ordering::SeqCst);
@ -294,7 +302,10 @@ macro_rules! make_timer {
}
fn clear_compare_flag() {
$timer.sr().modify(|r| r.set_ccif(1, false));
$timer.sr().write(|r| {
r.0 = !0;
r.set_ccif(1, false);
});
}
fn pend_interrupt() {
@ -312,13 +323,19 @@ macro_rules! make_timer {
fn on_interrupt() {
// Full period
if $timer.sr().read().uif() {
$timer.sr().modify(|r| r.set_uif(false));
$timer.sr().write(|r| {
r.0 = !0;
r.set_uif(false);
});
let prev = $overflow.fetch_add(1, Ordering::Relaxed);
assert!(prev % 2 == 1, "Monotonic must have missed an interrupt!");
}
// Half period
if $timer.sr().read().ccif(0) {
$timer.sr().modify(|r| r.set_ccif(0, false));
$timer.sr().write(|r| {
r.0 = !0;
r.set_ccif(0, false);
});
let prev = $overflow.fetch_add(1, Ordering::Relaxed);
assert!(prev % 2 == 0, "Monotonic must have missed an interrupt!");
}