From 1f6b6a42e5d581300dc3f72ebe489ea1380fe0ef Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Wed, 16 Oct 2024 12:29:51 -0700 Subject: [PATCH] Update support/example for ESP32-C3 to use latest versions of dependencies (#975) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Update `rtic` package to use latest version of `esp32c3` dependency * Update `rtic-macros` ESP32-C3 bindings to reflect changes in HAL * Update the ESP32-C3 examples to use latest versions of all dependencies * Update changelogs * adjust expected qemu output, add compile-time checks * remove runtime checks, this is checked at compile time * fix expected qemu output * Clean up interrupt enable code a bit * Update `rtic-monotonic` to use the latest PAC for ESP32-C3 * Update `CHANGELOG.md` for `rtic-monotonic` * ci: esp32c3: Format runner.sh * ci: esp32c3: Default to silent boot export DEBUGGING while running to get verbose boot env DEBUGGING=1 cargo xtask ... * ci: esp32c3: Update expected example output --------- Co-authored-by: onsdagens Co-authored-by: Henrik Tjäder --- ci/expected/esp32c3/monotonic.run | 28 - ci/expected/esp32c3/sw_and_hw.run | 28 - examples/esp32c3/Cargo.lock | 700 +++++++++++--------- examples/esp32c3/Cargo.toml | 11 +- examples/esp32c3/examples/sw_and_hw.rs | 13 +- examples/esp32c3/runner.sh | 20 +- rtic-macros/CHANGELOG.md | 4 + rtic-macros/src/codegen/bindings/esp32c3.rs | 12 +- rtic-monotonics/CHANGELOG.md | 4 + rtic-monotonics/Cargo.toml | 2 +- rtic-monotonics/src/esp32c3.rs | 41 +- rtic/CHANGELOG.md | 1 + rtic/Cargo.toml | 2 +- rtic/src/export/riscv_esp32c3.rs | 37 +- 14 files changed, 463 insertions(+), 440 deletions(-) diff --git a/ci/expected/esp32c3/monotonic.run b/ci/expected/esp32c3/monotonic.run index 9bf82bd6cc..7e3decc7fc 100644 --- a/ci/expected/esp32c3/monotonic.run +++ b/ci/expected/esp32c3/monotonic.run @@ -1,33 +1,5 @@ QEMU 8.2.0 monitor - type 'help' for more information (qemu) q -ESP-ROM:esp32c3-api1-20210207 -Build:Feb 7 2021 -rst:0x1 (POWERON),boot:0x8 (SPI_FAST_FLASH_BOOT) -SPIWP:0xee -mode:DIO, clock div:2 -load:0x3fcd5820,len:0x1714 -load:0x403cc710,len:0x968 -load:0x403ce710,len:0x2f9c -entry 0x403cc710 -I (0) boot: ESP-IDF v5.1.2-342-gbcf1645e44 2nd stage bootloader -I (0) boot: compile time Dec 12 2023 10:50:58 -I (0) boot: chip revision: v0.3 -I (0) boot.esp32c3: SPI Speed : 40MHz -I (0) boot.esp32c3: SPI Mode : SLOW READ -I (0) boot.esp32c3: SPI Flash Size : 4MB -I (0) boot: Enabling RNG early entropy source... -I (1) boot: Partition Table: -I (1) boot: ## Label Usage Type ST Offset Length -I (1) boot: 0 nvs WiFi data 01 02 00009000 00006000 -I (1) boot: 1 phy_init RF data 01 01 0000f000 00001000 -I (1) boot: 2 factory factory app 00 00 00010000 003f0000 -I (1) boot: End of partition table -I (1) esp_image: REDACTED -I (3) esp_image: REDACTED -I (3) esp_image: REDACTED -I (8) esp_image: REDACTED -I (11) boot: Loaded app from partition at offset 0x10000 -I (11) boot: Disabling RNG early entropy source... init hello from bar hello from baz diff --git a/ci/expected/esp32c3/sw_and_hw.run b/ci/expected/esp32c3/sw_and_hw.run index 9421a9c6d9..693b053de2 100644 --- a/ci/expected/esp32c3/sw_and_hw.run +++ b/ci/expected/esp32c3/sw_and_hw.run @@ -1,33 +1,5 @@ QEMU 8.2.0 monitor - type 'help' for more information (qemu) q -ESP-ROM:esp32c3-api1-20210207 -Build:Feb 7 2021 -rst:0x1 (POWERON),boot:0x8 (SPI_FAST_FLASH_BOOT) -SPIWP:0xee -mode:DIO, clock div:2 -load:0x3fcd5820,len:0x1714 -load:0x403cc710,len:0x968 -load:0x403ce710,len:0x2f9c -entry 0x403cc710 -I (0) boot: ESP-IDF v5.1.2-342-gbcf1645e44 2nd stage bootloader -I (0) boot: compile time Dec 12 2023 10:50:58 -I (0) boot: chip revision: v0.3 -I (0) boot.esp32c3: SPI Speed : 40MHz -I (0) boot.esp32c3: SPI Mode : SLOW READ -I (0) boot.esp32c3: SPI Flash Size : 4MB -I (0) boot: Enabling RNG early entropy source... -I (1) boot: Partition Table: -I (1) boot: ## Label Usage Type ST Offset Length -I (1) boot: 0 nvs WiFi data 01 02 00009000 00006000 -I (1) boot: 1 phy_init RF data 01 01 0000f000 00001000 -I (1) boot: 2 factory factory app 00 00 00010000 003f0000 -I (1) boot: End of partition table -I (1) esp_image: REDACTED -I (3) esp_image: REDACTED -I (3) esp_image: REDACTED -I (8) esp_image: REDACTED -I (11) boot: Loaded app from partition at offset 0x10000 -I (11) boot: Disabling RNG early entropy source... init Inside high prio task, press button now! Leaving high prio task. diff --git a/examples/esp32c3/Cargo.lock b/examples/esp32c3/Cargo.lock index 5aaf0e1ba2..115b7d7e39 100644 --- a/examples/esp32c3/Cargo.lock +++ b/examples/esp32c3/Cargo.lock @@ -3,25 +3,59 @@ version = 3 [[package]] -name = "aho-corasick" -version = "1.1.3" +name = "anstream" +version = "0.6.15" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "8e60d3430d3a69478ad0993f19238d2df97c507009a52b3c10addcd7f6bcb916" +checksum = "64e15c1ab1f89faffbf04a634d5e1962e9074f2741eef6d97f3c4e322426d526" dependencies = [ - "memchr", + "anstyle", + "anstyle-parse", + "anstyle-query", + "anstyle-wincon", + "colorchoice", + "is_terminal_polyfill", + "utf8parse", +] + +[[package]] +name = "anstyle" +version = "1.0.8" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "1bec1de6f59aedf83baf9ff929c98f2ad654b97c9510f4e70cf6f661d49fd5b1" + +[[package]] +name = "anstyle-parse" +version = "0.2.5" +source = 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"registry+https://github.com/rust-lang/crates.io-index" -checksum = "904102108b780c9a5e3275c5f3c63dc348ec43ae5da5237868515498b447d51a" +checksum = "2ceb69c1487b78d83531c5d94fb81d0dceef1ccb0affba29f29420b1f72d3ddb" dependencies = [ + "anyhow", "bare-metal", - "core-isa-parser", + "document-features", + "enum-as-inner", "minijinja", "r0", + "serde", + "strum", + "toml", + "xtensa-lx", "xtensa-lx-rt-proc-macros", ] [[package]] name = "xtensa-lx-rt-proc-macros" -version = "0.2.1" +version = "0.2.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "082cdede098bbec9af15b0e74085e5f3d16f2923597de7aed7b8112003af2da7" +checksum = "11277b1e4cbb7ffe44678c668518b249c843c81df249b8f096701757bc50d7ee" dependencies = [ "darling", "proc-macro2", "quote", - "syn 2.0.53", + "syn 2.0.77", ] diff --git a/examples/esp32c3/Cargo.toml b/examples/esp32c3/Cargo.toml index adb0ece33b..ae2024dc8a 100644 --- a/examples/esp32c3/Cargo.toml +++ b/examples/esp32c3/Cargo.toml @@ -7,18 +7,17 @@ license = "MIT OR Apache-2.0" [workspace] [dependencies] -rtic = {path = "../../rtic/"} +rtic = { path = "../../rtic/" } rtic-monotonics = {path = "../../rtic-monotonics/"} -esp-hal = { version = "0.16.1", features = ["esp32c3", "direct-vectoring", "interrupt-preemption"] } -esp-backtrace = { version = "0.11.0", features = [ +esp-hal = { version = "0.20.1", features = ["esp32c3"] } +esp-backtrace = { version = "0.14.0", features = [ "esp32c3", "panic-handler", "exception-handler", "println", ] } - -esp32c3 = {version = "0.22.0", features = ["critical-section"]} -esp-println = { version = "0.9.0", features = ["esp32c3", "uart"] } +esp32c3 = {version = "0.25.0", features = ["critical-section"]} +esp-println = { version = "0.11.0", features = ["esp32c3"] } [features] test-critical-section = [] diff --git a/examples/esp32c3/examples/sw_and_hw.rs b/examples/esp32c3/examples/sw_and_hw.rs index 42dd0ecd53..1aeae8fc85 100644 --- a/examples/esp32c3/examples/sw_and_hw.rs +++ b/examples/esp32c3/examples/sw_and_hw.rs @@ -4,17 +4,17 @@ mod app { use esp_backtrace as _; use esp_hal::{ - gpio::{Event, Gpio9, Input, PullDown, IO}, + gpio::{Event, GpioPin, Input, Io, Pull}, peripherals::Peripherals, - prelude::*, }; use esp_println::println; + #[shared] struct Shared {} #[local] struct Local { - button: Gpio9>, + button: Input<'static, GpioPin<9>>, } // do nothing in init @@ -22,14 +22,14 @@ mod app { fn init(_: init::Context) -> (Shared, Local) { println!("init"); let peripherals = Peripherals::take(); - let io = IO::new(peripherals.GPIO, peripherals.IO_MUX); - let mut button = io.pins.gpio9.into_pull_down_input(); + let io = Io::new_no_bind_interrupt(peripherals.GPIO, peripherals.IO_MUX); + let mut button = Input::new(io.pins.gpio9, Pull::Up); button.listen(Event::FallingEdge); foo::spawn().unwrap(); (Shared {}, Local { button }) } - #[idle()] + #[idle] fn idle(_: idle::Context) -> ! { println!("idle"); loop {} @@ -46,6 +46,7 @@ mod app { } println!("Leaving high prio task."); } + #[task(priority = 2)] async fn bar(_: bar::Context) { println!("Inside low prio task, press button now!"); diff --git a/examples/esp32c3/runner.sh b/examples/esp32c3/runner.sh index 3310acaf94..5dcbde414b 100755 --- a/examples/esp32c3/runner.sh +++ b/examples/esp32c3/runner.sh @@ -1,8 +1,7 @@ #!/bin/bash -if [ $# -eq 0 ] - then - echo "No arguments supplied! Provide path to ELF as argument" +if [ $# -eq 0 ]; then + echo "No arguments supplied! Provide path to ELF as argument" fi outputfilenamecargo=$1 @@ -19,13 +18,20 @@ espflash save-image --chip esp32c3 --merge "$outputfilenamecargo" "$outputfilena esptool.py image_info --version 2 "$outputfilename" 1>&2 # Run in QEMU -$qemuexec -nographic -monitor tcp:127.0.0.1:55555,server,nowait -icount 3 -machine esp32c3 -drive file="$outputfilename",if=mtd,format=raw -serial file:"$logfile" & +$qemuexec -nographic -monitor tcp:127.0.0.1:55555,server,nowait -icount 3 -machine esp32c3 -drive file="$outputfilename",if=mtd,format=raw -serial file:"$logfile" & # Let it run sleep 3s # Kill QEMU nicely by sending 'q' (quit) over tcp echo q | nc -N 127.0.0.1 55555 -# Output that will be compared, remove the esp_image segments as they change -# between runs -cat "$logfile" | sed 's/esp_image: .*$/esp_image: REDACTED/' + +# Output that will be compared must be printed to stdout + +# Make boot phase silent, for debugging change, run with e.g. $ `env DEBUGGING=true` cargo xtask.... +if [ -n "${DEBUGGING}" ]; then + # Debugging: strip leading "I (xyz)" where xyz is an incrementing number, and esp_image specifics + sed -e 's/esp_image: .*$/esp_image: REDACTED/' -e 's/I\s\([0-9]*\)(.*)/\1/' < $logfile +else + tail -n +12 "$logfile" | sed -e '/I\s\([0-9]*\)(.*)/d' +fi diff --git a/rtic-macros/CHANGELOG.md b/rtic-macros/CHANGELOG.md index 5a69d42817..dd9dceaf04 100644 --- a/rtic-macros/CHANGELOG.md +++ b/rtic-macros/CHANGELOG.md @@ -14,6 +14,10 @@ For each category, *Added*, *Changed*, *Fixed* add new entries at the top! - Fix codegen emitting unqualified `Result` - Improve error output for prios > dispatchers +### Fixed + +- Fix interrupt handlers when targeting esp32c3 and using latest version of esp-hal + ## [v2.1.0] - 2024-02-27 ### Added diff --git a/rtic-macros/src/codegen/bindings/esp32c3.rs b/rtic-macros/src/codegen/bindings/esp32c3.rs index 254b0f5e28..4caaa35f13 100644 --- a/rtic-macros/src/codegen/bindings/esp32c3.rs +++ b/rtic-macros/src/codegen/bindings/esp32c3.rs @@ -80,11 +80,13 @@ mod esp32c3 { } stmts } + pub fn pre_init_enable_interrupts(app: &App, analysis: &CodegenAnalysis) -> Vec { let mut stmts = vec![]; - let mut curr_cpu_id: u8 = 1; //cpu interrupt id 0 is reserved + let mut curr_cpu_id: u8 = 16; // cpu interrupt ids 0-15 are reserved let rt_err = util::rt_err_ident(); let max_prio: usize = 15; //unfortunately this is not part of pac, but we know that max prio is 15. + let min_prio: usize = 1; let interrupt_ids = analysis.interrupts.iter().map(|(p, (id, _))| (p, id)); // Unmask interrupts and set their priorities for (&priority, name) in interrupt_ids.chain( @@ -95,9 +97,11 @@ mod esp32c3 { let es = format!( "Maximum priority used by interrupt vector '{name}' is more than supported by hardware" ); + let es_zero = format!("Priority {priority} used by interrupt vector '{name}' is less than supported by hardware"); // Compile time assert that this priority is supported by the device stmts.push(quote!( const _: () = if (#max_prio) <= #priority as usize { ::core::panic!(#es); }; + const _: () = if (#min_prio) > #priority as usize { ::core::panic!(#es_zero);}; )); stmts.push(quote!( rtic::export::enable( @@ -218,14 +222,14 @@ mod esp32c3 { static RTIC_ASYNC_MAX_LOGICAL_PRIO: u8 = #max; )] } + pub fn handler_config( app: &App, analysis: &CodegenAnalysis, dispatcher_name: Ident, ) -> Vec { let mut stmts = vec![]; - let mut curr_cpu_id = 1; - //let mut ret = ""; + let mut curr_cpu_id = 16; // cpu interrupt ids 0-15 are reserved let interrupt_ids = analysis.interrupts.iter().map(|(p, (id, _))| (p, id)); for (_, name) in interrupt_ids.chain( app.hardware_tasks @@ -233,7 +237,7 @@ mod esp32c3 { .filter_map(|task| Some((&task.args.priority, &task.args.binds))), ) { if *name == dispatcher_name { - let ret = &("cpu_int_".to_owned() + &curr_cpu_id.to_string() + "_handler"); + let ret = &("interrupt".to_owned() + &curr_cpu_id.to_string()); stmts.push(quote!(#[export_name = #ret])); } curr_cpu_id += 1; diff --git a/rtic-monotonics/CHANGELOG.md b/rtic-monotonics/CHANGELOG.md index fa185d6fd7..6e18648795 100644 --- a/rtic-monotonics/CHANGELOG.md +++ b/rtic-monotonics/CHANGELOG.md @@ -11,6 +11,10 @@ For each category, *Added*, *Changed*, *Fixed* add new entries at the top! - RP235x support +### Changed + +- Update `esp32c3` dependency + ## v2.0.2 - 2024-07-05 ### Added diff --git a/rtic-monotonics/Cargo.toml b/rtic-monotonics/Cargo.toml index 953c658734..56f319f879 100644 --- a/rtic-monotonics/Cargo.toml +++ b/rtic-monotonics/Cargo.toml @@ -67,7 +67,7 @@ stm32-metapac = { version = "15.0.0", optional = true } imxrt-ral = { version = "0.5.3", optional = true } -esp32c3 = {version = "0.22.0", optional = true } +esp32c3 = {version = "0.25.0", optional = true } riscv = {version = "0.11.1", optional = true } diff --git a/rtic-monotonics/src/esp32c3.rs b/rtic-monotonics/src/esp32c3.rs index 61e044e2d6..924df2c2c4 100644 --- a/rtic-monotonics/src/esp32c3.rs +++ b/rtic-monotonics/src/esp32c3.rs @@ -1,4 +1,4 @@ -//! [`Monotonic`](rtic_time::Monotonic) implementation for ESP32C3's SYSTIMER. +//! [`Monotonic`](rtic_time::Monotonic) implementation for ESP32-C3's SYSTIMER. //! //! Always runs at a fixed rate of 16 MHz. //! @@ -26,7 +26,7 @@ //! } //! ``` -/// Common definitions and traits for using the RP2040 timer monotonic +/// Common definitions and traits for using the ESP32-C3 timer monotonic pub mod prelude { pub use crate::esp32c3_systimer_monotonic; @@ -61,7 +61,7 @@ impl TimerBackend { .cpu_int_enable() .modify(|r, w| w.bits((1 << cpu_interrupt_number) | r.bits())); //enable the CPU interupt. let intr = INTERRUPT_CORE0::ptr(); - let intr_prio_base = (*intr).cpu_int_pri_0().as_ptr(); + let intr_prio_base = (*intr).cpu_int_pri(0).as_ptr(); intr_prio_base .offset(cpu_interrupt_number) @@ -84,18 +84,11 @@ impl TimerQueueBackend for TimerBackend { peripherals .SYSTIMER .unit0_op() - .write(|w| w.timer_unit0_update().set_bit()); + .write(|w| w.update().set_bit()); // this must be polled until value is valid - while { - peripherals - .SYSTIMER - .unit0_op() - .read() - .timer_unit0_value_valid() - == false - } {} - let instant: u64 = (peripherals.SYSTIMER.unit0_value_lo().read().bits() as u64) - | ((peripherals.SYSTIMER.unit0_value_hi().read().bits() as u64) << 32); + while peripherals.SYSTIMER.unit0_op().read().value_valid() == false {} + let instant: u64 = (peripherals.SYSTIMER.unit_value(0).lo().read().bits() as u64) + | ((peripherals.SYSTIMER.unit_value(0).hi().read().bits() as u64) << 32); instant } @@ -103,19 +96,19 @@ impl TimerQueueBackend for TimerBackend { let systimer = unsafe { esp32c3::Peripherals::steal() }.SYSTIMER; systimer .target0_conf() - .write(|w| w.target0_timer_unit_sel().set_bit()); + .write(|w| w.timer_unit_sel().set_bit()); systimer .target0_conf() - .write(|w| w.target0_period_mode().clear_bit()); + .write(|w| w.period_mode().clear_bit()); systimer - .target0_lo() + .trgt(0) + .lo() .write(|w| unsafe { w.bits((instant & 0xFFFFFFFF).try_into().unwrap()) }); systimer - .target0_hi() + .trgt(0) + .hi() .write(|w| unsafe { w.bits((instant >> 32).try_into().unwrap()) }); - systimer - .comp0_load() - .write(|w| w.timer_comp0_load().set_bit()); //sync period to comp register + systimer.comp0_load().write(|w| w.load().set_bit()); //sync period to comp register systimer.conf().write(|w| w.target0_work_en().set_bit()); systimer.int_ena().write(|w| w.target0().set_bit()); } @@ -129,13 +122,13 @@ impl TimerQueueBackend for TimerBackend { fn pend_interrupt() { extern "C" { - fn cpu_int_31_handler(); + fn interrupt31(); } //run the timer interrupt handler in a critical section to emulate a max priority //interrupt. //since there is no hardware support for pending a timer interrupt. riscv::interrupt::disable(); - unsafe { cpu_int_31_handler() }; + unsafe { interrupt31() }; unsafe { riscv::interrupt::enable() }; } @@ -162,7 +155,7 @@ macro_rules! esp32c3_systimer_monotonic { /// /// This method must be called only once. pub fn start(timer: esp32c3::SYSTIMER) { - #[export_name = "cpu_int_31_handler"] + #[export_name = "interrupt31"] #[allow(non_snake_case)] unsafe extern "C" fn Systimer() { use $crate::TimerQueueBackend; diff --git a/rtic/CHANGELOG.md b/rtic/CHANGELOG.md index ac5436eb73..d7203fa1b3 100644 --- a/rtic/CHANGELOG.md +++ b/rtic/CHANGELOG.md @@ -13,6 +13,7 @@ For each category, *Added*, *Changed*, *Fixed* add new entries at the top! - Use `riscv-slic` from `crates.io` - Replace `atomic-polyfill` with `portable-atomic` - Remove unused dependency `rtic-monotonics` +- Updated esp32c3 dependency to v0.25.0 ## [v2.1.1] - 2024-03-13 diff --git a/rtic/Cargo.toml b/rtic/Cargo.toml index 7170fc4de3..adaa056ecd 100644 --- a/rtic/Cargo.toml +++ b/rtic/Cargo.toml @@ -26,7 +26,7 @@ name = "rtic" [dependencies] riscv-slic = { version = "0.1.1", optional = true } -esp32c3 = { version = "0.22.0", optional = true } +esp32c3 = { version = "0.25.0", optional = true } riscv = { version = "0.11.0", optional = true } cortex-m = { version = "0.7.0", optional = true } bare-metal = "1.0.0" diff --git a/rtic/src/export/riscv_esp32c3.rs b/rtic/src/export/riscv_esp32c3.rs index 5780d40729..1b0a91dbf3 100644 --- a/rtic/src/export/riscv_esp32c3.rs +++ b/rtic/src/export/riscv_esp32c3.rs @@ -1,7 +1,6 @@ -use esp32c3::INTERRUPT_CORE0; //priority threshold control +use esp32c3::INTERRUPT_CORE0; pub use esp32c3::{Interrupt, Peripherals}; -pub use riscv::interrupt; -pub use riscv::register::mcause; //low level interrupt enable/disable +pub use riscv::{interrupt, register::mcause}; #[cfg(all(feature = "riscv-esp32c3", not(feature = "riscv-esp32c3-backend")))] compile_error!("Building for the esp32c3, but 'riscv-esp32c3-backend not selected'"); @@ -138,28 +137,20 @@ pub fn unpend(int: Interrupt) { } pub fn enable(int: Interrupt, prio: u8, cpu_int_id: u8) { - const INTERRUPT_MAP_BASE: u32 = 0x600c2000; //this isn't exposed properly in the PAC, - //should maybe figure out a workaround that - //doesnt involve raw pointers. - //Again, this is how they do it in the HAL - //but i'm really not a fan. - let interrupt_number = int as isize; - let cpu_interrupt_number = cpu_int_id as isize; - unsafe { - let intr_map_base = INTERRUPT_MAP_BASE as *mut u32; - intr_map_base - .offset(interrupt_number) - .write_volatile(cpu_interrupt_number as u32); - //map peripheral interrupt to CPU interrupt + // Map the peripheral interrupt to a CPU interrupt: + (INTERRUPT_CORE0::ptr() as *mut u32) + .offset(int as isize) + .write_volatile(cpu_int_id as u32); + + // Set the interrupt's priority: + (*INTERRUPT_CORE0::ptr()) + .cpu_int_pri(cpu_int_id as usize) + .modify(|_, w| w.bits(prio as u32)); + + // Finally, enable the CPU interrupt: (*INTERRUPT_CORE0::ptr()) .cpu_int_enable() - .modify(|r, w| w.bits((1 << cpu_interrupt_number) | r.bits())); //enable the CPU interupt. - let intr = INTERRUPT_CORE0::ptr(); - let intr_prio_base = (*intr).cpu_int_pri_0().as_ptr(); - - intr_prio_base - .offset(cpu_interrupt_number) - .write_volatile(prio as u32); + .modify(|r, w| w.bits((1 << cpu_int_id) | r.bits())); } }