rtic/.gitignore

**/*.rs.bk
.#*
.gdb_history
/book/*/book
/target
Cargo.lock
*.hex
book-target/

.DS_Store
.vscode/
compile time verified ceilings 2017-04-10 05:42:17 +02:00			`*/.rs.bk`
drop the Static wrapper 2017-12-09 13:38:41 +01:00			`.#*`
update examples 2017-07-29 07:34:00 +02:00			`.gdb_history`
change layout of books 2019-02-11 21:40:53 +01:00			`/book/*/book`
v0.4.0 closes #32 closes #33 2018-11-03 17:02:41 +01:00			`/target`
initial commit 2017-03-05 06:26:14 +01:00			`Cargo.lock`
Make identifiers deterministic. 2019-01-17 02:36:55 +01:00			`*.hex`
Add check-book.sh script 2023-05-05 18:52:14 +02:00			`book-target/`
RISC-V support over CLINT (#815) * Rebase to master * using interrupt_mod * bug fixes * fix other backends * Add changelog * forgot about rtic-macros * backend-specific configuration * core peripherals optional over macro argument * pre_init_preprocessing binding * CI for RISC-V (WIP) * separation of concerns * add targets for RISC-V examples * remove qemu feature * prepare examples folder * move examples all together * move ci out of examples * minor changes * add cortex-m * new xtask: proof of concept * fix build.yml * feature typo * clean rtic examples * reproduce weird issue * remove unsafe code in user app * update dependencies * allow builds on riscv32imc * let's fix QEMU * Update .github/workflows/build.yml Co-authored-by: Henrik Tjäder <henrik@tjaders.com> * New build.rs * removing test features * adapt ui test to new version of clippy * add more examples to RISC-V backend * proper configuration of heapless for riscv32imc * opt-out examples for riscv32imc * point to new version of riscv-slic * adapt new macro bindings * adapt examples and CI to stable * fix cortex-m CI * Review --------- Co-authored-by: Henrik Tjäder <henrik@tjaders.com> 2024-03-20 21:06:47 +01:00
			`.DS_Store`
			`.vscode/`