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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="Module Control Register 2"><title>imxrt_ral::flexspi::MCR2 - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../../static.files/rustdoc-492a78a4a87dcc01.css"><meta name="rustdoc-vars" data-root-path="../../../" data-static-root-path="../../../static.files/" data-current-crate="imxrt_ral" data-themes="" data-resource-suffix="" data-rustdoc-version="1.82.0 (f6e511eec 2024-10-15)" data-channel="1.82.0" data-search-js="search-a99f1315e7cc5121.js" data-settings-js="settings-4313503d2e1961c2.js" ><script src="../../../static.files/storage-118b08c4c78b968e.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../../static.files/main-921df33f47b8780c.js"></script><noscript><link rel="stylesheet" href="../../../static.files/noscript-3b12f09e550e0385.css"></noscript><link rel="alternate icon" type="image/png" href="../../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../../imxrt_ral/index.html">imxrt_<wbr>ral</a><span class="version">0.5.3</span></h2></div><h2 class="location"><a href="#">Module MCR2</a></h2><div class="sidebar-elems"><section><ul class="block"><li><a href="#modules">Modules</a></li></ul></section><h2><a href="../index.html">In imxrt_<wbr>ral::<wbr>flexspi</a></h2></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><h1>Module <a href="../../index.html">imxrt_ral</a>::<wbr><a href="../index.html">flexspi</a>::<wbr><a class="mod" href="#">MCR2</a><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><span class="out-of-band"><a class="src" href="../../../src/imxrt_ral/blocks/imxrt1011/flexspi.rs.html#253">source</a> · <button id="toggle-all-docs" title="collapse all docs">[<span>−</span>]</button></span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>Module Control Register 2</p>
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</div></details><h2 id="modules" class="section-header">Modules<a href="#modules" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="mod" href="CLRAHBBUFOPT/index.html" title="mod imxrt_ral::flexspi::MCR2::CLRAHBBUFOPT">CLRAHBBUFOPT</a></div><div class="desc docblock-short">This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.</div></li><li><div class="item-name"><a class="mod" href="CLRLEARNPHASE/index.html" title="mod imxrt_ral::flexspi::MCR2::CLRLEARNPHASE">CLRLEARNPHASE</a></div><div class="desc docblock-short">The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately.</div></li><li><div class="item-name"><a class="mod" href="RESUMEWAIT/index.html" title="mod imxrt_ral::flexspi::MCR2::RESUMEWAIT">RESUMEWAIT</a></div><div class="desc docblock-short">Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.</div></li><li><div class="item-name"><a class="mod" href="SAMEDEVICEEN/index.html" title="mod imxrt_ral::flexspi::MCR2::SAMEDEVICEEN">SAMEDEVICEEN</a></div><div class="desc docblock-short">All external devices are same devices (both in types and size) for A1/A2/B1/B2.</div></li><li><div class="item-name"><a class="mod" href="SCKBDIFFOPT/index.html" title="mod imxrt_ral::flexspi::MCR2::SCKBDIFFOPT">SCKBDIFFOPT</a></div><div class="desc docblock-short">B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK). In this case, port B flash access is not available. After changing the value of this field, MCR0[SWRESET] should be set.</div></li></ul></section></div></main></body></html>
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