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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset."><title>rp2040_pac::ppb::aircr - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../../static.files/rustdoc-b0742ba02757f159.css"><meta name="rustdoc-vars" data-root-path="../../../" data-static-root-path="../../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.83.0 (90b35a623 2024-11-26)" data-channel="1.83.0" data-search-js="search-f0d225181b97f9a4.js" data-settings-js="settings-805db61a62df4bd2.js" ><script src="../../../static.files/storage-1d39b6787ed640ff.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../../static.files/main-f070b9041d14864c.js"></script><noscript><link rel="stylesheet" href="../../../static.files/noscript-0111fcff984fae8f.css"></noscript><link rel="alternate icon" type="image/png" href="../../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><div class="sidebar-elems"><section id="rustdoc-toc"><h2 class="location"><a href="#">Module aircr</a></h2><h3><a href="#structs">Module Items</a></h3><ul class="block"><li><a href="#structs" title="Structs">Structs</a></li><li><a href="#types" title="Type Aliases">Type Aliases</a></li></ul></section><div id="rustdoc-modnav"><h2><a href="../index.html">In rp2040_<wbr>pac::<wbr>ppb</a></h2></div></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><span class="rustdoc-breadcrumbs"><a href="../../index.html">rp2040_pac</a>::<wbr><a href="../index.html">ppb</a></span><h1>Module <span>aircr</span><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><rustdoc-toolbar></rustdoc-toolbar><span class="sub-heading"><a class="src" href="../../../src/rp2040_pac/ppb/aircr.rs.html#1-98">source</a> </span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.</p>
</div></details><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="struct" href="struct.AIRCR_SPEC.html" title="struct rp2040_pac::ppb::aircr::AIRCR_SPEC">AIRCR_<wbr>SPEC</a></div><div class="desc docblock-short">Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.</div></li></ul><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="type" href="type.ENDIANESS_R.html" title="type rp2040_pac::ppb::aircr::ENDIANESS_R">ENDIANESS_<wbr>R</a></div><div class="desc docblock-short">Field <code>ENDIANESS</code> reader - Data endianness implemented:<br />
0 = Little-endian.</div></li><li><div class="item-name"><a class="type" href="type.R.html" title="type rp2040_pac::ppb::aircr::R">R</a></div><div class="desc docblock-short">Register <code>AIRCR</code> reader</div></li><li><div class="item-name"><a class="type" href="type.SYSRESETREQ_R.html" title="type rp2040_pac::ppb::aircr::SYSRESETREQ_R">SYSRESETREQ_<wbr>R</a></div><div class="desc docblock-short">Field <code>SYSRESETREQ</code> reader - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device.</div></li><li><div class="item-name"><a class="type" href="type.SYSRESETREQ_W.html" title="type rp2040_pac::ppb::aircr::SYSRESETREQ_W">SYSRESETREQ_<wbr>W</a></div><div class="desc docblock-short">Field <code>SYSRESETREQ</code> writer - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device.</div></li><li><div class="item-name"><a class="type" href="type.VECTCLRACTIVE_R.html" title="type rp2040_pac::ppb::aircr::VECTCLRACTIVE_R">VECTCLRACTIVE_<wbr>R</a></div><div class="desc docblock-short">Field <code>VECTCLRACTIVE</code> reader - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack.</div></li><li><div class="item-name"><a class="type" href="type.VECTCLRACTIVE_W.html" title="type rp2040_pac::ppb::aircr::VECTCLRACTIVE_W">VECTCLRACTIVE_<wbr>W</a></div><div class="desc docblock-short">Field <code>VECTCLRACTIVE</code> writer - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack.</div></li><li><div class="item-name"><a class="type" href="type.VECTKEY_R.html" title="type rp2040_pac::ppb::aircr::VECTKEY_R">VECTKEY_<wbr>R</a></div><div class="desc docblock-short">Field <code>VECTKEY</code> reader - Register key:<br />
Reads as Unknown<br />
On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.</div></li><li><div class="item-name"><a class="type" href="type.VECTKEY_W.html" title="type rp2040_pac::ppb::aircr::VECTKEY_W">VECTKEY_<wbr>W</a></div><div class="desc docblock-short">Field <code>VECTKEY</code> writer - Register key:<br />
Reads as Unknown<br />
On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.</div></li><li><div class="item-name"><a class="type" href="type.W.html" title="type rp2040_pac::ppb::aircr::W">W</a></div><div class="desc docblock-short">Register <code>AIRCR</code> writer</div></li></ul></section></div></main></body></html>
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