rtic/2/api/search.desc/imxrt_ral/imxrt_ral-desc-3-.js

searchState.loadedDescShard("imxrt_ral", 3, "PMIC On Request Enable The value written to PK_EN will be …\nPMIC On Request Override The value written to PK_OVERRIDE …\nPower Glitch Enable By default the detection of a power …\nSecure Real Time Counter Enabled and Valid When set, the …\nIf this bit is 1, in the case of a security violation the …\nTurn off System Power Asserting this bit causes a signal …\nSmart PMIC enabled.\nDumb PMIC enabled.\nSRTC Time calibration is disabled.\nSRTC Time calibration is enabled.\n+0 counts per each 32768 ticks of the counter clock\n+1 counts per each 32768 ticks of the counter clock\n+15 counts per each 32768 ticks of the counter clock\n-16 counts per each 32768 ticks of the counter clock\n-15 counts per each 32768 ticks of the counter clock\n+2 counts per each 32768 ticks of the counter clock\n-2 counts per each 32768 ticks of the counter clock\n-1 counts per each 32768 ticks of the counter clock\nLP time alarm interrupt is disabled.\nLP time alarm interrupt is enabled.\nMC is disabled or invalid.\nMC is enabled and valid.\nSRTC is disabled or invalid.\nSRTC is enabled and valid.\nSRTC stays valid in the case of security violation.\nSRTC is invalidated in the case of security violation.\nLeave system power on.\nTurn off system power.\nGeneral Purpose Register When GPR_SL or GPR_HL bit is set, …\nGeneral Purpose Register When GPR_SL or GPR_HL bit is set, …\nGeneral Purpose Register When GPR_SL or GPR_HL bit is set, …\nGeneral Purpose Register Hard Lock When set, prevents any …\nLP Calibration Hard Lock When set, prevents any writes to …\nLP Security Violation Control Register Hard Lock When set, …\nLP Tamper Detectors Configuration Register Hard Lock When …\nMonotonic Counter Hard Lock When set, prevents any writes …\nMaster Key Select Hard Lock When set, prevents any writes …\nSecure Real Time Counter Hard Lock When set, prevents any …\nZeroizable Master Key Read Hard Lock When set, prevents …\nZeroizable Master Key Write Hard Lock When set, prevents …\nWrite access is allowed.\nWrite access is not allowed.\nWrite access is allowed.\nWrite access is not allowed.\nWrite access is allowed.\nWrite access is not allowed.\nWrite access is allowed.\nWrite access is not allowed.\nWrite access (increment) is allowed.\nWrite access (increment) is not allowed.\nWrite access is allowed.\nWrite access is not allowed.\nWrite access is allowed.\nWrite access is not allowed.\nRead access is allowed (only in software programming mode).\nRead access is not allowed.\nWrite access is allowed.\nWrite access is not allowed.\nMaster Key Select These bits select the SNVS Master Key …\nZeroizable Master Key Error Correcting Code Check Enable …\nZeroizable Master Key Error Correcting Code Value This …\nZeroizable Master Key hardware Programming mode When set, …\nZeroizable Master Key Valid When set, the ZMK value can be …\nSelect one time programmable master key.\nSelect zeroizable master key when MKS_EN bit is set .\nSelect combined master key when MKS_EN bit is set .\nZMK ECC check is disabled.\nZMK ECC check is enabled.\nZMK is in the software programming mode.\nZMK is in the hardware programming mode.\nZMK is not valid.\nZMK is valid.\nPower Glitch Detector Value\nMonotonic Counter bits The MC is incremented by one when: …\nMonotonic Counter Era Bits These bits are inputs to the …\nMonotonic Counter most-significant 16 Bits The MC is …\nEmergency Off This bit is set when a power off is …\nExternal Security Violation Detected Indicates that a …\nExternal Tampering 1 Detected\nLP Section is Non-Secured Indicates that LP section was …\nLP Section is Secured Indicates that the LP section is …\nLP Time Alarm\nMonotonic Counter Rollover\nPower Supply Glitch Detected 0 No power supply glitch. 1 …\nScan Exit Detected\nSet Power Off The SPO bit is set when the power button is …\nSecure Real Time Counter Rollover\nEmergency off was not detected.\nEmergency off was detected.\nNo external security violation.\nExternal security violation is detected.\nExte