2017-07-29 07:34:00 +02:00
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//! Real Time For the Masses (RTFM) framework for ARM Cortex-M microcontrollers
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2017-07-21 05:53:44 +02:00
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//!
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//! This crate is based on [the RTFM framework] created by the Embedded Systems
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//! group at [Luleå University of Technology][ltu], led by Prof. Per Lindgren,
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//! and uses a simplified version of the Stack Resource Policy as scheduling
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//! policy (check the [references] for details).
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//!
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//! [the RTFM framework]: http://www.rtfm-lang.org/
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//! [ltu]: https://www.ltu.se/?l=en
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//! [per]: https://www.ltu.se/staff/p/pln-1.11258?l=en
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//! [references]: ./index.html#references
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//!
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//! # Features
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//!
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//! - **Event triggered tasks** as the unit of concurrency.
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//! - Support for prioritization of tasks and, thus, **preemptive
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//! multitasking**.
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//! - **Efficient and data race free memory sharing** through fine grained *non
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//! global* critical sections.
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//! - **Deadlock free execution** guaranteed at compile time.
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//! - **Minimal scheduling overhead** as the scheduler has no "software
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//! component": the hardware does all the scheduling.
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//! - **Highly efficient memory usage**: All the tasks share a single call stack
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//! and there's no hard dependency on a dynamic memory allocator.
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//! - **All Cortex M devices are fully supported**.
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//! - This task model is amenable to known WCET (Worst Case Execution Time)
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//! analysis and scheduling analysis techniques. (Though we haven't yet
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//! developed Rust friendly tooling for that.)
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//!
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//! # Constraints
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//!
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//! - Tasks must run to completion. That's it, tasks can't contain endless
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//! loops. However, you can run an endless event loop in the `idle` function.
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//!
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//! - Task priorities must remain constant at runtime.
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//!
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//! # Dependencies
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//!
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2017-07-29 07:34:00 +02:00
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//! The application crate must depend on a device crate generated using
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//! [`svd2rust`] v0.11.x and the "rt" feature of that crate must be enabled. The
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//! SVD file used to generate the device crate *must* contain [`<cpu>`]
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//! information.
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2017-07-21 05:53:44 +02:00
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//!
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//! [`svd2rust`]: https://docs.rs/svd2rust/0..0/svd2rust/
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//! [`<cpu>`]: https://www.keil.com/pack/doc/CMSIS/SVD/html/elem_cpu.html
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2017-07-29 07:34:00 +02:00
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//!
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//! # More documentation
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//!
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//! The `app!` macro is documented [here](../cortex_m_rtfm_macros/fn.app.html).
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2017-07-21 05:53:44 +02:00
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//!
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//! # Examples
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//!
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2017-07-29 07:34:00 +02:00
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//! In increasing grade of complexity. See the [examples](./examples/index.html)
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2017-07-21 06:14:41 +02:00
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//! module.
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2017-07-21 05:53:44 +02:00
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#![deny(missing_docs)]
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#![deny(warnings)]
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2017-07-12 06:44:54 +02:00
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#![feature(proc_macro)]
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2017-03-05 06:26:14 +01:00
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#![no_std]
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extern crate cortex_m;
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2017-07-12 06:44:54 +02:00
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extern crate cortex_m_rtfm_macros;
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2017-07-27 18:37:58 +02:00
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extern crate rtfm_core;
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2017-04-14 16:45:50 +02:00
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extern crate static_ref;
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2017-03-05 06:26:14 +01:00
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2017-07-27 18:37:58 +02:00
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use core::u8;
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pub use rtfm_core::{Resource, Static, Threshold};
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2017-04-14 17:05:24 +02:00
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pub use cortex_m::asm::{bkpt, wfi};
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2017-07-21 06:14:41 +02:00
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pub use cortex_m_rtfm_macros::app;
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2017-07-27 18:37:58 +02:00
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use cortex_m::interrupt::{self, Nr};
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2017-07-04 18:26:11 +02:00
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#[cfg(not(armv6m))]
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2017-07-27 18:37:58 +02:00
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use cortex_m::register::basepri;
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2017-07-21 05:53:44 +02:00
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pub mod examples;
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2017-07-29 07:34:00 +02:00
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/// Executes the closure `f` in a preemption free context
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///
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/// During the execution of the closure no task can preempt the current task.
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2017-07-27 18:37:58 +02:00
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pub fn atomic<R, F>(t: &mut Threshold, f: F) -> R
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where
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F: FnOnce(&mut Threshold) -> R,
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{
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if t.value() == u8::MAX {
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f(t)
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} else {
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interrupt::disable();
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let r = f(&mut unsafe { Threshold::max() });
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unsafe { interrupt::enable() };
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r
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2017-07-21 05:53:44 +02:00
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}
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}
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2017-07-26 05:30:41 +02:00
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#[inline]
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2017-07-21 05:53:44 +02:00
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#[doc(hidden)]
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2017-07-24 03:51:37 +02:00
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pub unsafe fn claim<T, R, F>(
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data: T,
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2017-07-04 18:26:11 +02:00
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ceiling: u8,
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2017-07-27 22:15:19 +02:00
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_nvic_prio_bits: u8,
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2017-07-04 18:26:11 +02:00
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t: &mut Threshold,
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f: F,
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) -> R
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2017-04-21 07:24:54 +02:00
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where
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2017-07-24 03:51:37 +02:00
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F: FnOnce(T, &mut Threshold) -> R,
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2017-04-21 07:24:54 +02:00
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{
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2017-07-27 18:37:58 +02:00
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if ceiling > t.value() {
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2017-07-04 18:26:11 +02:00
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match () {
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#[cfg(armv6m)]
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2017-07-27 18:37:58 +02:00
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() => atomic(t, |t| f(data, t)),
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2017-07-04 18:26:11 +02:00
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#[cfg(not(armv6m))]
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() => {
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2017-07-27 22:15:19 +02:00
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let max_priority = 1 << _nvic_prio_bits;
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2017-07-27 21:59:31 +02:00
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2017-07-04 18:26:11 +02:00
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if ceiling == max_priority {
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2017-07-27 18:37:58 +02:00
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atomic(t, |t| f(data, t))
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2017-07-04 18:26:11 +02:00
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} else {
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let old = basepri::read();
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2017-07-27 22:15:19 +02:00
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let hw = (max_priority - ceiling) << (8 - _nvic_prio_bits);
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2017-07-27 18:37:58 +02:00
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basepri::write(hw);
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2017-07-24 03:51:37 +02:00
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let ret = f(data, &mut Threshold::new(ceiling));
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2017-07-04 18:26:11 +02:00
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basepri::write(old);
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ret
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}
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}
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2017-03-05 06:26:14 +01:00
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}
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2017-07-04 18:26:11 +02:00
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} else {
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2017-07-24 03:51:37 +02:00
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f(data, t)
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2017-03-05 06:26:14 +01:00
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}
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2017-03-10 05:59:50 +01:00
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}
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2017-03-05 06:26:14 +01:00
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2017-07-29 07:34:00 +02:00
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/// Sets an interrupt, that is a task, as pending
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2017-07-25 05:46:29 +02:00
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///
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2017-07-29 07:34:00 +02:00
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/// If the task priority is high enough the task will be serviced immediately,
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/// otherwise it will be serviced at some point after the current task ends.
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2017-07-07 06:25:29 +02:00
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pub fn set_pending<I>(interrupt: I)
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where
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I: Nr,
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{
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// NOTE(safe) atomic write
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let nvic = unsafe { &*cortex_m::peripheral::NVIC.get() };
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nvic.set_pending(interrupt);
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}
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