2019-06-13 23:56:59 +02:00
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use core::{
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cell::Cell,
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sync::atomic::{AtomicBool, Ordering},
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};
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2018-11-03 17:02:41 +01:00
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2020-12-12 23:24:54 +01:00
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pub use crate::tq::{NotReady, TimerQueue};
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2020-10-01 20:01:25 +02:00
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pub use bare_metal::CriticalSection;
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2018-11-03 17:02:41 +01:00
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pub use cortex_m::{
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2019-06-13 23:56:59 +02:00
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asm::wfi,
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interrupt,
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2021-09-28 10:18:43 +02:00
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peripheral::{scb::SystemHandler, DWT, NVIC, SCB, SYST},
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2019-06-13 23:56:59 +02:00
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Peripherals,
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2018-11-03 17:02:41 +01:00
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};
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2021-08-16 15:37:39 +02:00
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pub use heapless::sorted_linked_list::SortedLinkedList;
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2021-04-03 19:30:34 +02:00
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pub use heapless::spsc::Queue;
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pub use heapless::BinaryHeap;
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2021-02-18 19:30:59 +01:00
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pub use rtic_monotonic as monotonic;
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2018-11-03 17:02:41 +01:00
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2021-04-03 19:30:34 +02:00
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pub type SCFQ<const N: usize> = Queue<u8, N>;
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pub type SCRQ<T, const N: usize> = Queue<(T, u8), N>;
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2018-11-03 17:02:41 +01:00
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2021-09-14 16:13:28 +02:00
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#[cfg(armv7m)]
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use cortex_m::register::basepri;
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2018-11-03 17:02:41 +01:00
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#[cfg(armv7m)]
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#[inline(always)]
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2019-04-21 20:02:59 +02:00
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pub fn run<F>(priority: u8, f: F)
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2018-11-03 17:02:41 +01:00
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where
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F: FnOnce(),
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{
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2019-04-21 20:02:59 +02:00
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if priority == 1 {
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2020-09-01 19:04:55 +02:00
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// If the priority of this interrupt is `1` then BASEPRI can only be `0`
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2019-04-21 20:02:59 +02:00
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f();
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unsafe { basepri::write(0) }
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} else {
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let initial = basepri::read();
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f();
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unsafe { basepri::write(initial) }
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}
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2018-11-03 17:02:41 +01:00
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}
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#[cfg(not(armv7m))]
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#[inline(always)]
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2019-04-21 20:02:59 +02:00
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pub fn run<F>(_priority: u8, f: F)
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2018-11-03 17:02:41 +01:00
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where
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F: FnOnce(),
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{
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f();
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}
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2019-06-13 23:56:59 +02:00
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pub struct Barrier {
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inner: AtomicBool,
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}
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impl Barrier {
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pub const fn new() -> Self {
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Barrier {
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inner: AtomicBool::new(false),
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}
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}
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pub fn release(&self) {
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self.inner.store(true, Ordering::Release)
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}
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pub fn wait(&self) {
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while !self.inner.load(Ordering::Acquire) {}
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}
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}
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2019-02-16 00:22:00 +01:00
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// Newtype over `Cell` that forbids mutation through a shared reference
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pub struct Priority {
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inner: Cell<u8>,
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}
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impl Priority {
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2020-10-13 16:16:33 +02:00
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/// Create a new Priority
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///
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/// # Safety
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///
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/// Will overwrite the current Priority
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2019-02-16 00:22:00 +01:00
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#[inline(always)]
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pub unsafe fn new(value: u8) -> Self {
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2019-02-16 00:26:07 +01:00
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Priority {
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inner: Cell::new(value),
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}
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2019-02-16 00:22:00 +01:00
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}
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2020-10-13 16:16:33 +02:00
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/// Change the current priority to `value`
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2020-09-01 19:04:55 +02:00
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// These two methods are used by `lock` (see below) but can't be used from the RTIC application
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2019-02-16 00:22:00 +01:00
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#[inline(always)]
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fn set(&self, value: u8) {
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self.inner.set(value)
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}
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2020-10-13 16:16:33 +02:00
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/// Get the current priority
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2019-02-16 00:22:00 +01:00
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#[inline(always)]
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fn get(&self) -> u8 {
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self.inner.get()
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}
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}
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2018-11-03 17:02:41 +01:00
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#[inline(always)]
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pub fn assert_send<T>()
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where
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T: Send,
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{
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}
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#[inline(always)]
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pub fn assert_sync<T>()
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where
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T: Sync,
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{
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}
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2018-11-04 18:50:42 +01:00
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2020-12-10 20:33:13 +01:00
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#[inline(always)]
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pub fn assert_monotonic<T>()
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where
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2021-02-18 19:30:59 +01:00
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T: monotonic::Monotonic,
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2020-12-10 20:33:13 +01:00
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{
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}
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2020-10-13 16:16:33 +02:00
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/// Lock the resource proxy by setting the BASEPRI
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/// and running the closure with interrupt::free
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///
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/// # Safety
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///
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/// Writing to the BASEPRI
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/// Dereferencing a raw pointer
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2018-11-04 18:50:42 +01:00
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#[cfg(armv7m)]
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#[inline(always)]
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2019-04-21 20:02:59 +02:00
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pub unsafe fn lock<T, R>(
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2018-11-04 18:50:42 +01:00
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ptr: *mut T,
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2019-02-16 00:22:00 +01:00
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priority: &Priority,
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2018-11-04 18:50:42 +01:00
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ceiling: u8,
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nvic_prio_bits: u8,
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2019-04-21 20:02:59 +02:00
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f: impl FnOnce(&mut T) -> R,
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) -> R {
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2018-11-04 18:50:42 +01:00
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let current = priority.get();
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2019-04-21 20:02:59 +02:00
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if current < ceiling {
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2018-11-04 18:50:42 +01:00
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if ceiling == (1 << nvic_prio_bits) {
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2019-06-13 23:56:59 +02:00
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priority.set(u8::max_value());
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2018-11-04 18:50:42 +01:00
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let r = interrupt::free(|_| f(&mut *ptr));
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priority.set(current);
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r
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} else {
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priority.set(ceiling);
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basepri::write(logical2hw(ceiling, nvic_prio_bits));
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let r = f(&mut *ptr);
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basepri::write(logical2hw(current, nvic_prio_bits));
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priority.set(current);
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r
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}
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} else {
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f(&mut *ptr)
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}
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}
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2020-10-13 16:16:33 +02:00
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/// Lock the resource proxy by setting the PRIMASK
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/// and running the closure with interrupt::free
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///
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/// # Safety
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///
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/// Writing to the PRIMASK
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/// Dereferencing a raw pointer
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2018-11-04 18:50:42 +01:00
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#[cfg(not(armv7m))]
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#[inline(always)]
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2019-04-21 20:02:59 +02:00
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pub unsafe fn lock<T, R>(
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2018-11-04 18:50:42 +01:00
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ptr: *mut T,
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2019-02-16 00:22:00 +01:00
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priority: &Priority,
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2018-11-04 18:50:42 +01:00
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ceiling: u8,
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_nvic_prio_bits: u8,
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2019-04-21 20:02:59 +02:00
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f: impl FnOnce(&mut T) -> R,
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) -> R {
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2018-11-04 18:50:42 +01:00
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let current = priority.get();
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2019-04-21 20:02:59 +02:00
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if current < ceiling {
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2019-06-13 23:56:59 +02:00
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priority.set(u8::max_value());
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2018-11-04 18:50:42 +01:00
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let r = interrupt::free(|_| f(&mut *ptr));
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priority.set(current);
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r
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} else {
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f(&mut *ptr)
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}
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}
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#[inline]
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2019-04-21 20:02:59 +02:00
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pub fn logical2hw(logical: u8, nvic_prio_bits: u8) -> u8 {
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2018-11-04 18:50:42 +01:00
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((1 << nvic_prio_bits) - logical) << (8 - nvic_prio_bits)
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}
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