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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="QSPI flash execute-in-place block"><title>rp2040_pac::xip_ctrl - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../static.files/rustdoc-b0742ba02757f159.css"><meta name="rustdoc-vars" data-root-path="../../" data-static-root-path="../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.83.0 (90b35a623 2024-11-26)" data-channel="1.83.0" data-search-js="search-f0d225181b97f9a4.js" data-settings-js="settings-805db61a62df4bd2.js" ><script src="../../static.files/storage-1d39b6787ed640ff.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../static.files/main-f070b9041d14864c.js"></script><noscript><link rel="stylesheet" href="../../static.files/noscript-0111fcff984fae8f.css"></noscript><link rel="alternate icon" type="image/png" href="../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><div class="sidebar-elems"><section id="rustdoc-toc"><h2 class="location"><a href="#">Module xip_<wbr>ctrl</a></h2><h3><a href="#modules">Module Items</a></h3><ul class="block"><li><a href="#modules" title="Modules">Modules</a></li><li><a href="#structs" title="Structs">Structs</a></li><li><a href="#types" title="Type Aliases">Type Aliases</a></li></ul></section><div id="rustdoc-modnav"><h2 class="in-crate"><a href="../index.html">In crate rp2040_<wbr>pac</a></h2></div></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><span class="rustdoc-breadcrumbs"><a href="../index.html">rp2040_pac</a></span><h1>Module <span>xip_ctrl</span><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><rustdoc-toolbar></rustdoc-toolbar><span class="sub-heading"><a class="src" href="../../src/rp2040_pac/xip_ctrl.rs.html#1-153">source</a> </span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>QSPI flash execute-in-place block</p>
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</div></details><h2 id="modules" class="section-header">Modules<a href="#modules" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="mod" href="ctr_acc/index.html" title="mod rp2040_pac::xip_ctrl::ctr_acc">ctr_acc</a></div><div class="desc docblock-short">Cache Access counter<br />
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A 32 bit saturating counter that increments upon each XIP access,<br />
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whether the cache is hit or not. This includes noncacheable accesses.<br />
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Write any value to clear.</div></li><li><div class="item-name"><a class="mod" href="ctr_hit/index.html" title="mod rp2040_pac::xip_ctrl::ctr_hit">ctr_hit</a></div><div class="desc docblock-short">Cache Hit counter<br />
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A 32 bit saturating counter that increments upon each cache hit,<br />
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i.e. when an XIP access is serviced directly from cached data.<br />
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Write any value to clear.</div></li><li><div class="item-name"><a class="mod" href="ctrl/index.html" title="mod rp2040_pac::xip_ctrl::ctrl">ctrl</a></div><div class="desc docblock-short">Cache control</div></li><li><div class="item-name"><a class="mod" href="flush/index.html" title="mod rp2040_pac::xip_ctrl::flush">flush</a></div><div class="desc docblock-short">Cache Flush control</div></li><li><div class="item-name"><a class="mod" href="stat/index.html" title="mod rp2040_pac::xip_ctrl::stat">stat</a></div><div class="desc docblock-short">Cache Status</div></li><li><div class="item-name"><a class="mod" href="stream_addr/index.html" title="mod rp2040_pac::xip_ctrl::stream_addr">stream_<wbr>addr</a></div><div class="desc docblock-short">FIFO stream address</div></li><li><div class="item-name"><a class="mod" href="stream_ctr/index.html" title="mod rp2040_pac::xip_ctrl::stream_ctr">stream_<wbr>ctr</a></div><div class="desc docblock-short">FIFO stream control</div></li><li><div class="item-name"><a class="mod" href="stream_fifo/index.html" title="mod rp2040_pac::xip_ctrl::stream_fifo">stream_<wbr>fifo</a></div><div class="desc docblock-short">FIFO stream data<br />
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Streamed data is buffered here, for retrieval by the system DMA.<br />
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This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing<br />
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the DMA to bus stalls caused by other XIP traffic.</div></li></ul><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="struct" href="struct.RegisterBlock.html" title="struct rp2040_pac::xip_ctrl::RegisterBlock">Register<wbr>Block</a></div><div class="desc docblock-short">Register block</div></li></ul><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="type" href="type.CTRL.html" title="type rp2040_pac::xip_ctrl::CTRL">CTRL</a></div><div class="desc docblock-short">CTRL (rw) register accessor: Cache control</div></li><li><div class="item-name"><a class="type" href="type.CTR_ACC.html" title="type rp2040_pac::xip_ctrl::CTR_ACC">CTR_ACC</a></div><div class="desc docblock-short">CTR_ACC (rw) register accessor: Cache Access counter<br />
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A 32 bit saturating counter that increments upon each XIP access,<br />
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whether the cache is hit or not. This includes noncacheable accesses.<br />
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Write any value to clear.</div></li><li><div class="item-name"><a class="type" href="type.CTR_HIT.html" title="type rp2040_pac::xip_ctrl::CTR_HIT">CTR_HIT</a></div><div class="desc docblock-short">CTR_HIT (rw) register accessor: Cache Hit counter<br />
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A 32 bit saturating counter that increments upon each cache hit,<br />
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i.e. when an XIP access is serviced directly from cached data.<br />
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Write any value to clear.</div></li><li><div class="item-name"><a class="type" href="type.FLUSH.html" title="type rp2040_pac::xip_ctrl::FLUSH">FLUSH</a></div><div class="desc docblock-short">FLUSH (rw) register accessor: Cache Flush control</div></li><li><div class="item-name"><a class="type" href="type.STAT.html" title="type rp2040_pac::xip_ctrl::STAT">STAT</a></div><div class="desc docblock-short">STAT (r) register accessor: Cache Status</div></li><li><div class="item-name"><a class="type" href="type.STREAM_ADDR.html" title="type rp2040_pac::xip_ctrl::STREAM_ADDR">STREAM_<wbr>ADDR</a></div><div class="desc docblock-short">STREAM_ADDR (rw) register accessor: FIFO stream address</div></li><li><div class="item-name"><a class="type" href="type.STREAM_CTR.html" title="type rp2040_pac::xip_ctrl::STREAM_CTR">STREAM_<wbr>CTR</a></div><div class="desc docblock-short">STREAM_CTR (rw) register accessor: FIFO stream control</div></li><li><div class="item-name"><a class="type" href="type.STREAM_FIFO.html" title="type rp2040_pac::xip_ctrl::STREAM_FIFO">STREAM_<wbr>FIFO</a></div><div class="desc docblock-short">STREAM_FIFO (r) register accessor: FIFO stream data<br />
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Streamed data is buffered here, for retrieval by the system DMA.<br />
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This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing<br />
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the DMA to bus stalls caused by other XIP traffic.</div></li></ul></section></div></main></body></html>
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