mirror/rtic
1
0
Fork 0
mirror of https://github.com/rtic-rs/rtic.git synced 2024-12-27 20:39:33 +01:00
Code Issues Projects Releases Packages Wiki Activity
rtic/dev/api/rp2040_pac/pll_sys/cs/index.html

14 lines
6.3 KiB
HTML
Raw Permalink Normal View History

deploy: 1a1237690cf676733579ffde0f507a00950e474e
2024-12-06 14:35:18 +01:00
<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz"><title>rp2040_pac::pll_sys::cs - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../../static.files/rustdoc-b0742ba02757f159.css"><meta name="rustdoc-vars" data-root-path="../../../" data-static-root-path="../../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.83.0 (90b35a623 2024-11-26)" data-channel="1.83.0" data-search-js="search-f0d225181b97f9a4.js" data-settings-js="settings-805db61a62df4bd2.js" ><script src="../../../static.files/storage-1d39b6787ed640ff.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../../static.files/main-f070b9041d14864c.js"></script><noscript><link rel="stylesheet" href="../../../static.files/noscript-0111fcff984fae8f.css"></noscript><link rel="alternate icon" type="image/png" href="../../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><div class="sidebar-elems"><section id="rustdoc-toc"><h2 class="location"><a href="#">Module cs</a></h2><h3><a href="#structs">Module Items</a></h3><ul class="block"><li><a href="#structs" title="Structs">Structs</a></li><li><a href="#types" title="Type Aliases">Type Aliases</a></li></ul></section><div id="rustdoc-modnav"><h2><a href="../index.html">In rp2040_<wbr>pac::<wbr>pll_<wbr>sys</a></h2></div></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><span class="rustdoc-breadcrumbs"><a href="../../index.html">rp2040_pac</a>::<wbr><a href="../index.html">pll_sys</a></span><h1>Module <span>cs</span><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><rustdoc-toolbar></rustdoc-toolbar><span class="sub-heading"><a class="src" href="../../../src/rp2040_pac/pll_sys/cs.rs.html#1-85">source</a> </span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>Control and Status<br />
GENERAL CONSTRAINTS:<br />
Reference clock frequency min=5MHz, max=800MHz<br />
Feedback divider min=16, max=320<br />
VCO frequency min=750MHz, max=1600MHz</p>
</div></details><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="struct" href="struct.CS_SPEC.html" title="struct rp2040_pac::pll_sys::cs::CS_SPEC">CS_SPEC</a></div><div class="desc docblock-short">Control and Status<br />
GENERAL CONSTRAINTS:<br />
Reference clock frequency min=5MHz, max=800MHz<br />
Feedback divider min=16, max=320<br />
VCO frequency min=750MHz, max=1600MHz</div></li></ul><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="type" href="type.BYPASS_R.html" title="type rp2040_pac::pll_sys::cs::BYPASS_R">BYPASS_<wbr>R</a></div><div class="desc docblock-short">Field <code>BYPASS</code> reader - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.</div></li><li><div class="item-name"><a class="type" href="type.BYPASS_W.html" title="type rp2040_pac::pll_sys::cs::BYPASS_W">BYPASS_<wbr>W</a></div><div class="desc docblock-short">Field <code>BYPASS</code> writer - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.</div></li><li><div class="item-name"><a class="type" href="type.LOCK_R.html" title="type rp2040_pac::pll_sys::cs::LOCK_R">LOCK_R</a></div><div class="desc docblock-short">Field <code>LOCK</code> reader - PLL is locked</div></li><li><div class="item-name"><a class="type" href="type.R.html" title="type rp2040_pac::pll_sys::cs::R">R</a></div><div class="desc docblock-short">Register <code>CS</code> reader</div></li><li><div class="item-name"><a class="type" href="type.REFDIV_R.html" title="type rp2040_pac::pll_sys::cs::REFDIV_R">REFDIV_<wbr>R</a></div><div class="desc docblock-short">Field <code>REFDIV</code> reader - Divides the PLL input reference clock.<br />
Behaviour is undefined for div=0.<br />
PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.</div></li><li><div class="item-name"><a class="type" href="type.REFDIV_W.html" title="type rp2040_pac::pll_sys::cs::REFDIV_W">REFDIV_<wbr>W</a></div><div class="desc docblock-short">Field <code>REFDIV</code> writer - Divides the PLL input reference clock.<br />
Behaviour is undefined for div=0.<br />
PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.</div></li><li><div class="item-name"><a class="type" href="type.W.html" title="type rp2040_pac::pll_sys::cs::W">W</a></div><div class="desc docblock-short">Register <code>CS</code> writer</div></li></ul></section></div></main></body></html>
Reference in a new issue Copy permalink